Jie-Hong R. Jiang, Chih-Chun Lee, Alan Mishchenko, and Chung-Yang (Ric) Huang, “To SAT or Not to SAT: Scalable Exploration of Functional Dependency,” IEEE Transactions on Computers (TCOMP), vol. 59, no. 4, pages 457-467, Apr. 2010
R.C.-Y. Huang and K.-T. Cheng, “Using Word-Level ATPG and Modular Arithmetic Constraint-Solving Techniques for Assertion Property Checking,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, , Volume 20, No. 3, pp. 381-391, Mar. 2001
S.-Y. Huang, K.-T. Cheng, K.-C. Chen, C.-Y. Huang, and F. Brewer, “AQUILA: An Equivalence Checking System for Large Sequential Designs,” IEEE Trans. on Computer, Vol. 49, No. 5, pp. 443-464, May 2000
Conference & proceeding papers:
Yu-Fu Yeh, Chung-Yang (Ric) Huang, Chi-An Wu and Hsin-Cheng Lin, “Speeding Up MPSoC Virtual Platform Simulation by Ultra Synchronization Checking Method,” Proc. ACM/IEEE Design, Automation, and Test in Europe (DATE) conference, Mar. 2011
Shao-Lun Huang, Chi-An Wu, Kai-Fu Tang, Chang-Hong Hsu and Chung-Yang (Ric) Huang, “A Robust ECO Engine by Resource-Constraint-Aware Technology Mapping and Incremental Routing Optimization,” Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2011
Chung-Yang (Ric) Huang, Yu-Fan Yin, Chih-Jen Hsu, Thomas B. Huang and Ting-Mao Chang, “SoC HW/SW Verification and Validation,” Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2011
Chun-Nan Chou, Chang-Hong Hsu, Yueh-Tung Chao and Chung-Yang (Ric) Huang, “Formal Deadlock Checking on High-Level SystemC Designs,” Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2010
Bo-Han Wu, Chun-Ju Yang, Chung-Yang (Ric) Huang and Jie-Hong (Roland) Jiang, “A Robust Functional ECO Engine by SAT Proof Minimization and Interpolation Techniques,” Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2010
Hu-Hsi Yeh and Chung-Yang (Ric) Huang, “Automatic Constraint Generation for Guided Random Simulation,” Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2010
Chin-Chia Nien, Shih-Heng Tsai, and Chung-Yang (Ric) Huang, “A Unified Multi-Corner Multi-Mode Static Timing Analysis Engine,” Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2010
Kuen-Huei Lin, Siao-Jie Cai, and Chung-Yang (Ric) Huang, “Speeding Up SoC Virtual Platform Simulation by Data-Dependency-Aware Synchronization and Scheduling,” Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2010
Chih-Jen Hsu, Shao-Lun Huang, Chia-An Wu and Chung-Yang (Ric) Huang, “Interpolant Generation without Constructing Resolution Graph,” Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2009
Chi-An Wu, Ting-Hao Lin, Shao-Lun Huang, and Chung-Yang (Ric) Huang, “SAT-Controlled Redundancy Addition and Removal - A Novel Circuit Restructuring Technique,” Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 2009
Kuen-Huei Lin, Siao-Jie Cai, and Chung-Yang (Ric) Huang, “Speeding Up SoC Virtual Platform Simulation by Data-Dependency Aware Virtual Synchronization,” International SoC Design Conference (ISoCC), Korea, Nov. 2008
Chao-Yue (Colby) Lai, Chung-Yang (Ric) Huang, and Kei-Yong Khoo, “Improving Constant-Coefficient Multiplier Verification by Partial Product Identification,” Design Automation and Test in Europe (DATE), Munich, Germany, Mar. 2008
Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang (Ric) Huang, and A. Mishchenko, “Scalable Exploration of Functional Dependency by Interpolation and Incremental SAT Solving,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, USA, Nov. 2007
Hsing-Chih Hung, Chi-Wen Chang, Tin-Hao Lin, and Chung-Yang (Ric) Huang, “QuteIP: An IP Qualification Framework for System on Chip,” IEEE SoC Conference (SOCC), Hsin-Chu, Taiwan, Aug. 2007
Chi-An Wu, Ting-Hao Lin, Chih-Chun Lee and Chung-Yang (Ric) Huang, “QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure,” Design Automation and Test in Europe (DATE) Conference, Nice, France, Apr. 2007
Feng Lu, Li-C. Wang, K-T. Cheng, and Ric C-Y. Huang, “A Circuit SAT Solver with Signal Correlation Guided Learning,” Proc. Design Automation & Test Conference, Europe, Mar. 2003
G. Parthasarathy, K-T. Cheng, C-Y Huang, “An Analysis of ATPG and SAT algorithms for Formal Verification,” Proc. International High Level Design Validation and Test Workshop, pp. 177-182, Nov. 2001
R.C.-Y. Huang, B. Yang, H.-C. Tsai, and K.-T. Cheng, “Static Property Checking Using ATPG vs. BDD Techniques,” Proc. International Test Conference, pp. 309-316, Oct. 2000
R.C.-Y. Huang and K.-T. Cheng, “Assertion Checking by Combined Word-level ATPG and Modular Arithmetic Constraint-Solving Techniques,” Proc. Design Automation Conference, pp. 118-123, Jun. 2000
R.C.-Y. Huang and K.-T. Cheng, “Solving Constraint Satisfiability Problem for Automatic Generation of Design Verification Vectors,” Proc. International High Level Design Validation and Test Workshop, pp. 30-36, Nov. 1999
R.C.-Y. Huang and K.-T. Cheng, “A New Extended Finite State Machine (EFSM) Model for RTL Design Verification,” Proc. International High Level Design Validation and Test Workshop, pp. 47-53, Nov. 1998
R.C.-Y. Huang, Y. Wang, and K.-T. Cheng, “Libra - A Library-Independent Framework for Post-Layout Performance Optimization,” Proc. International Symposium on Physical Design, pp. 135-140, Apr. 1998