黃鐘揚教授的個人資料 - Profile of Chung-Yang Huang

黃鐘揚 Chung-Yang Huang

國立臺灣大學電機工程學系 教授
國立台灣大學電子工程學研究所教授
Professor, Department of Electrical Engineering, National Taiwan University
Professor, Graduate Institute of Electronics Engineering, National Taiwan University

主要研究領域:

(1) SoC 電路設計驗證, (2) AI 輔助電路設計自動化與驗證, (3) 3D-IC 電路設計流程與驗證, (4) 量子電路設計合成與最佳化

Major Research Areas:

(1) SoC Design Verification, (2) AI-Powered Design for Verifiability, (3) 3D-IC Design Flow and Verification , and (4) Quantum Circuit Synthesis and Optimization

研究領域摘要:

 

Design Verification Lab (DVLab)

本實驗室主要之研究領域為系統晶片之設計驗證以及量子電路之設計最佳化，其中的項目包括：

  • 核心驗證引擎之研究與開發
  • GenAI 輔助之 IC 設計與驗證
  • 3D-IC 系統晶片設計流程與驗證
  • 量子電路設計之合成與最佳化

綜合以上之研究，本實驗室開發了兩套開源工具系統：

Research Summary:

Design Verification Lab (DVLab)

NTU Design Verification Lab focuses on research in system-on-chip (SoC) design verification and quantum circuit optimization. Key areas of research include:

  • Development and enhancement of core verification engines
  • GenAI-powered IC design and verification
  • 3D-IC design flow and verification
  • Synthesis and optimization of quantum circuit designs

Building on these research areas, the lab has developed two major tool systems:

Photo of Chung-Yang Huang

代表性著作 Selected Publication

  1. M-T Lau, C-Y Cheng, C-H Lu, C-H Chuang, Y-H Kuo, H-C Yang, C-T Kuo, H-Y Chen, C-Y Tung, C-E Tsai, G-H Chen, L-K Lin, C-H Wang, T-H Wang, C-Y (Ric) Huang, “Qsyn: A Developer-Friendly Quantum Circuit Synthesis Framework for NISQ Era and Beyond,” International Conference for Quantum Computing and Engineering, Nov. 2024
  2. Wang,Luo,Chien,Wang,Wang,Lin,Jiang,Huang, “Compatible Equivalence Checking of X-Valued Circuits,” 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1, Munich, Germany, Nov. 2021
  3. Cheng-Yin Wu, Chi-An Wu, Chien-Yu Lai, Chung-Yang (Ric) Huang, “A Counterexample-Guided Interpolant Generation Algorithm for SAT-Based Model Checking,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 33, 1846, Dec. 2014
  4. Bo-Han Wu, Chun-Ju Yang, and Chung-Yang (Ric) Huang, “A High-Throughput and Arbitrary-Distribution Pattern Generator for the Constrained Random Verification,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 33, 139, Jan. 2014
  5. Yu-Fu Yeh, Hsin-Cheng Lin, and Chung-Yang (Ric) Huang, “An Ultra Synchronization Checking Method with Trace‐Driven Simulation for Fast and Accurate MPSoC Virtual Platform Simulation,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 32, 928, Jun. 2013
  6. Shao-Lun Huang, Wei-Hsun Lin, Po-Kai Huang, Chung-Yang (Ric) Huang, “Match and Replace : A Functional ECO Engine for Multi-Error Circuit Rectification,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 32, 467, Mar. 2013
  7. Yu-Fu Yeh, Chung-Yang (Ric) Huang, Chi-An Wu and Hsin-Cheng Lin, “Speeding Up MPSoC Virtual Platform Simulation by Ultra Synchronization Checking Method,” Proc. ACM/IEEE Design, Automation, and Test in Europe (DATE) conference, Mar. 2011
  8. Shao-Lun Huang, Chi-An Wu, Kai-Fu Tang, Chang-Hong Hsu and Chung-Yang (Ric) Huang, “A Robust ECO Engine by Resource-Constraint-Aware Technology Mapping and Incremental Routing Optimization,” Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2011
  9. Chung-Yang (Ric) Huang, Yu-Fan Yin, Chih-Jen Hsu, Thomas B. Huang and Ting-Mao Chang, “SoC HW/SW Verification and Validation,” Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2011
  10. Chun-Nan Chou, Chang-Hong Hsu, Yueh-Tung Chao and Chung-Yang (Ric) Huang, “Formal Deadlock Checking on High-Level SystemC Designs,” Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2010
  11. Bo-Han Wu, Chun-Ju Yang, Chung-Yang (Ric) Huang and Jie-Hong (Roland) Jiang, “A Robust Functional ECO Engine by SAT Proof Minimization and Interpolation Techniques,” Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2010
  12. Jie-Hong R. Jiang, Chih-Chun Lee, Alan Mishchenko, and Chung-Yang (Ric) Huang, “To SAT or Not to SAT: Scalable Exploration of Functional Dependency,” IEEE Transactions on Computers (TCOMP), vol. 59, no. 4, pages 457-467, Apr. 2010
  13. Hu-Hsi Yeh and Chung-Yang (Ric) Huang, “Automatic Constraint Generation for Guided Random Simulation,” Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2010
  14. Chin-Chia Nien, Shih-Heng Tsai, and Chung-Yang (Ric) Huang, “A Unified Multi-Corner Multi-Mode Static Timing Analysis Engine,” Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2010
  15. Kuen-Huei Lin, Siao-Jie Cai, and Chung-Yang (Ric) Huang, “Speeding Up SoC Virtual Platform Simulation by Data-Dependency-Aware Synchronization and Scheduling,” Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 2010
  16. Chih-Jen Hsu, Shao-Lun Huang, Chia-An Wu and Chung-Yang (Ric) Huang, “Interpolant Generation without Constructing Resolution Graph,” Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), Nov. 2009
  17. Shih-Heng Tsai and Chung-Yang (Ric) Huang, “A False-Path Aware Formal Static Timing Analyzer Considering Simultaneous Input Transitions,” IEEE/ACM Design Automation Conference (DAC), Jun. 2009
  18. Chi-An Wu, Ting-Hao Lin, Shao-Lun Huang, and Chung-Yang (Ric) Huang, “SAT-Controlled Redundancy Addition and Removal - A Novel Circuit Restructuring Technique,” Asia and South Pacific Design Automation Conference (ASP-DAC), Yokohama, Japan, Jan. 2009
  19. Kuen-Huei Lin, Siao-Jie Cai, and Chung-Yang (Ric) Huang, “Speeding Up SoC Virtual Platform Simulation by Data-Dependency Aware Virtual Synchronization,” International SoC Design Conference (ISoCC), Korea, Nov. 2008
  20. Chao-Yue (Colby) Lai, Chung-Yang (Ric) Huang, and Kei-Yong Khoo, “Improving Constant-Coefficient Multiplier Verification by Partial Product Identification,” Design Automation and Test in Europe (DATE), Munich, Germany, Mar. 2008
  21. Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang (Ric) Huang, and A. Mishchenko, “Scalable Exploration of Functional Dependency by Interpolation and Incremental SAT Solving,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), San Jose, USA, Nov. 2007
  22. Hsing-Chih Hung, Chi-Wen Chang, Tin-Hao Lin, and Chung-Yang (Ric) Huang, “QuteIP: An IP Qualification Framework for System on Chip,” IEEE SoC Conference (SOCC), Hsin-Chu, Taiwan, Aug. 2007
  23. Chi-An Wu, Ting-Hao Lin, Chih-Chun Lee and Chung-Yang (Ric) Huang, “QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure,” Design Automation and Test in Europe (DATE) Conference, Nice, France, Apr. 2007
  24. Chung-Yang (Ric) Huang, “Solving Constraint Satisfiability Problem For Automatic Generation of Design Verification Vectors,” US. No. 7073143, Jul. 2006
  25. Chung-Yang (Ric) Huang, “Non-Assignable Signal Support During Formal Verification Of Circuit Designs,” US, No. 6618841, Sept. 2003
  26. Feng Lu, Li-C. Wang, K-T. Cheng, and Ric C-Y. Huang, “A Circuit SAT Solver with Signal Correlation Guided Learning,” Proc. Design Automation & Test Conference, Europe, Mar. 2003
  27. G. Parthasarathy, K-T. Cheng, C-Y Huang, “An Analysis of ATPG and SAT algorithms for Formal Verification,” Proc. International High Level Design Validation and Test Workshop, pp. 177-182, Nov. 2001
  28. R.C.-Y. Huang and K.-T. Cheng, “Using Word-Level ATPG and Modular Arithmetic Constraint-Solving Techniques for Assertion Property Checking,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, , Volume 20, No. 3, pp. 381-391, Mar. 2001
  29. R.C.-Y. Huang, B. Yang, H.-C. Tsai, and K.-T. Cheng, “Static Property Checking Using ATPG vs. BDD Techniques,” Proc. International Test Conference, pp. 309-316, Oct. 2000
  30. R.C.-Y. Huang and K.-T. Cheng, “Assertion Checking by Combined Word-level ATPG and Modular Arithmetic Constraint-Solving Techniques,” Proc. Design Automation Conference, pp. 118-123, Jun. 2000
  31. S.-Y. Huang, K.-T. Cheng, K.-C. Chen, C.-Y. Huang, and F. Brewer, “AQUILA: An Equivalence Checking System for Large Sequential Designs,” IEEE Trans. on Computer, Vol. 49, No. 5, pp. 443-464, May 2000
  32. R.C.-Y. Huang and K.-T. Cheng, “Solving Constraint Satisfiability Problem for Automatic Generation of Design Verification Vectors,” Proc. International High Level Design Validation and Test Workshop, pp. 30-36, Nov. 1999
  33. R.C.-Y. Huang and K.-T. Cheng, “A New Extended Finite State Machine (EFSM) Model for RTL Design Verification,” Proc. International High Level Design Validation and Test Workshop, pp. 47-53, Nov. 1998
  34. R.C.-Y. Huang, Y. Wang, and K.-T. Cheng, “Libra - A Library-Independent Framework for Post-Layout Performance Optimization,” Proc. International Symposium on Physical Design, pp. 135-140, Apr. 1998
  35. Tseng,Lin,Hsu,Huang, “Joint Sequence Learning and Cross-Modality Convolution for 3D Biomedical Segmentation,” 2017 IEEE Conference on Computer Vision and Pattern Recognition (CVPR), Honolulu, HI