Rong Jiang, Wenyin Fu and Charlie Chung-Ping Chen, “EPEEC: A Compact Eddy-Current-Aware Reluctance-Based Macromodel for High-Speed Interconnects above Lossy Multilayer Substrate,” IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), 2005
Lizheng Zhang, Weijen Chen, Yuhen Hu and Charlie Chungping Chen, “Statistical Static Timing Analysis with Conditional Linear MAX/MIN Approximation and Extended Canonical Model,” IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), 2005
Jeng-Laing Tsai, Tsung-Hao Chen, and Charlie Chung-Ping Chen, “Zero-Skew Clock-Tree Optimization with Buffer-Insertion/Sizing and Wire-Sizing,” IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 23, No. 4, pp. 565-572, Apr. 2004
Yu-Min Lee, Yahong Cao, Tsung-Hao Chen, Janet Wang and Charlie Chung-Ping Chen, “HiPRIME: Hierarchical and Passivity Preserved Interconnect Macromodeling Engine for RLKC Power Delivery,” IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), 2004
1. Yu-Min Lee and Charlie Chung-Ping Chen,, “The Power Grid Transient Simulation in Linear Time based on 3D Alternating-Direction-Implicit Method,” IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 22, No. 11, pp1545-1550,, Nov. 2003
2. Ting-Yuan Wang and Charlie Chung-Ping Chen,, “Thermal-ADI: A Linear-Time Chip-Level Dynamic Thermal Simulation Algorithm Based on Alternating-Direction-Implicit (ADI) Method,” IEEE Transaction on Very Large Scale Integration Systems (TVLSI),, Vol. 11, No. 4,, pp691- 700, Aug. 2003
3. Tsung-Hao Chen, Clement Luk, and Charlie Chung-Ping Chen,, “INDUCTWISE: Inductance-Wise Interconnect Simulator and Extractor,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD),, Vol. 22, No. 7,, pp884-894,, Jul. 2003
4. Ting-Yuan Wang and Charlie Chung-Ping Chen,, “3-D Thermal-ADI: a linear-time chip level transient thermal simulator,” IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 21, No. 11,, pp1343 -1352,, Nov. 2002
6. Yu-Min Lee, Charlie Chung-Ping Chen, and D. F. Wong, “Optimal Wire-sizing Function under the Elmore Delay Model with Bounded Wiresizes,” IEEE Transactions on Circuits & Systems-I (TCAS-I), Vol. 49, No. 11,, pp1671-1677,, Nov. 2002
Yu-Min Lee and Charlie Chung-Ping Chen, “Power Grid Transient Simulation in Linear Time based on Transmission-Line-Modeling Alternating-Direction-Implicit Method,” IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 21, No. 11, pp1343 -1352, Nov. 2002
7. Chung-Ping Chen, Chris C. N. Chu, and D. F. Wong,, “Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation,” IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD), Vol. 18, No. 7, pp1014-1025,, Jul. 1999
Conference & proceeding papers:
Jeng-Liang Tsai, DongHyun Baik, Charlie Chung-Ping Chen and Kewal K. Saluja, “False Path and Clock Scheduling Based Yield-Aware Gate Sizing,” VLSI Design, 2005
Jeng-Liang Tsai and Charlie Chung-Ping Chen, “Process-Variation Robust and Low-Power Zero-Skew Buffered Clock-Tree Synthesis Using Projected Scan-Line Sampling,” ASPDAC, 2005
Lizheng Zhang, Yu-Hen Hu and Charlie Chung-Ping Chen, “Block-Based Statistical Timing Analysis with Extended Canonical Timing Model,” ASPDAC, 2005
Lizheng Zhang, Yu-Hen Hu and Charlie Chung-Ping Chen, “Wave-Pipelined On-Chip Global Interconnect,” ASPDAC, 2005
Rong Jiang and Charlie Chung-Ping Chen, “Comprehensive Frequency Dependent Interconnect Extraction and Evaluction Methodology,” ASPDAC, 2005
Hsinwei Chou, Yu-Hao Wang and Charlie Chung-Ping Chen, “Fast and Effective Gate-Sizing with Multiple-Vt Assignment using Generalized Lagrangian Relaxation,” ASPDAC, 2005
Lizheng Zhang, Weijen Chen, Yu-Hen Hu and Charlie Chung-Ping Chen, “Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model,” DATE, 2005
Qi-Wei Kuo, Vikas Sharma and Charlie Chung-Ping Chen, “Substrate-Bias Optimized 0.18um 2.5 GHz 32-bit adder with Post-Manufacture Tunable Clock,” VLSI-TSA-DAT, 2005
Vikas Sharma, Chien-Liang Chen and Charlie Chung-Ping Chen, “1-V 7-mW Dual-Band Fast-Locked Frequency Synthesizer,” GLSVLSI, 2005
Rong Jiang and Charlie Chung-Ping Chen, “ICCAP: A Linear Time Sparse Transformation and Reordering Algorithm for 3D BEM Capacitance Extraction,” DAC, 2005
Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner and Charlie Chung-Ping Chen, “Correlation-Preserved Non-Gaussian Statistical Timing Analysis with Quadratic Timing Model,” DAC, 2005
Jeng-Liang Tsai, Lizheng Zhang and Charlie Chung-Ping Chen, “Statistical Timing Analysis Driven Post-Silicon-Tunable Clock-Tree Synthesis,” ICCAD, 2005
Sanghamitra Roy, Weijen Chen and Charlie Chung-Ping Chen, “ConvexFit: An Optimal Minimum-Error Convex Fitting and Smoothing Algorithm with Application to Gate-Sizing,” ICCAD, 2005
Rong Jiang, Wenyin Fu, Janet Meiling Wang and Charlie Chung-Ping Chen, “Efficient Statistical Capacitance Variability Modeling with Orthogonal Principle Factor Analysis,” ICCAD, 2005
Rong Jiang, Yu-hao Wang, and Charlie Chung-Ping Chen, “Linear Time Capacitance Extraction based on Implicit Congruence Transformation,” International Microwave Symposium (IMS), 2005
Lizheng Zhang, Yuhen Hu, and Charlie Chung-Ping Chen, “Wave-pipelined On-Chip Global Interconnect,” ACM/IEEE TAU Workshop on Timing Issues in the Specification and Synthesis of Digital Systems, 2004
Rong Jiang and Charlie Chung-Ping Chen, “Realizable Reduction for Electromagnetically Coupled RLMC Interconnects,” Design, Automation and Test in Europe Conference and Exhibition (DATE), 2004
Rong Jiang and Charlie Chung-Ping Chen, “SCORE: SPICE Compatible Reluctance Extraction,” Design, Automation and Test in Europe Conference and Exhibition (DATE), 2004
[26] Ting-Yuan Wang, Jeng-Liang Tsai, and Charlie Chung-Ping Chen, “Thermal and Power Integrity based Power/Ground Networks Optimization,” Design, Automation and Test in Europe Conference and Exhibition (DATE), 2004
Ting-Yuan Wang and Charlie Chung-Ping Chen, “SPICE-Compatible Thermal Simulation with Lumped Circuit Modeling for Thermal Reliability Analysis based on Model Reduction,” 5th International Symposium on Quality Electronic Design (ISQED), 2004
Ting-Yuan Wang, Jeng-Liang Tsai, and Charlie Chung-Ping Chen, “Power-Delivery Networks Optimization with Thermal Reliability Integrity,” ACM International Symposium on Physical Design (ISPD), 2004
Rong Jiang and Charlie Chung-Ping Chen, “ESPRIT: A Compact Reluctance Based Interconnect Model Considering Lossy Substrate Eddy Current,” International Microwave Symposium (IMS), 2004
Lizheng Zhang, Yu Hen Hu, and Charlie Chung-Ping Chen, “Statistical Timing Analysis in Sequential Circuit for On-Chip Global Interconnect Pipelining,” IEEE/ACM Design Automation Conference (DAC), 2004
Rong Jiang and Charlie Chung-Ping Chen, “EPEEC: A Compact Reluctance Based Interconnect Model Considering Lossy Substrate Eddy Currents,” IEEE Custom Integrated Circuits Conference (CICC), 2004
Lizheng Zhang, Yu-Hen Hu and Charlie Chung-Ping Chen, “Statistical Timing Analysis with AMECT: Asymptotic MAX/MIN Approximation and Extended Canonical Timing Model,” The 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), 2004
Hsinwei Chou and Charlie Chung-Ping Chen, “A ROBDD-Based Generalized Nodal Control Scheme for Standby Leakage Power Reduction,” The 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), 2004
Hsinwei Chou, Yu-Hao Wang and Charlie Chung-Ping Chen, “LARTTE: A Posynomial-Based Lagrangian Relaxation Tuning Tool for Fast and Effective Gate-Sizing and Multiple Vt Assignment,” The 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI), 2004
Jeng-Liang Tsai, DongHyun Baik, Charlie Chung-Ping Chen and Kewal K. Saluja, “A Yield Improvement Methodology Using Pre- and Post-Silicon Statistical Clock Scheduling,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2004
Tsung-Hao Chen, Jeng-Liang Tsai, Charlie Chung-Ping Chen and Tanay Karnik, “HiSIM: Hierarchical Interconnect-Centric Circuit Simulator,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2004
2. Rong Jiang, Tsung-Hao Chen, and Charlie Chung-Ping Chen,, “PODEA: POwer Delivery Efficient Analysis with Realizable Model Reduction,” IEEE International Symposium on Circuits and Systems (ISCAS, May 2003
3. Ting-Yuan Wang, Yu-Min Lee, and Charlie Chung-Ping Chen,, “3D Thermal-ADI: An Efficient Chip-Level Transient Thermal Simulator,” ACM International Symposium on Physical Design (ISPD), Apr. 2003
4. Jeng-Laing Tsai, Tsung-Hao Chen, and Charlie Chung-Ping Chen,, “Epsilon-Optimal Zero-Skew Clock Tree Wire-Sizing in Pseudo-Polynomial Time,” ACM International Symposium on Physical Design (ISPD),, Apr. 2003
Yu-Min Lee and Charlie Chung-Ping Chen,, “The Power Grid Transient Simulation in Linear Time based on 3D Alternating-Direction-Implicit Method,” Design, Automation and Test in Europe Conference and Exhibition (DATE), Feb. 2003
1. Tsung-Hao Chen, Clement Luk, and Charlie Chung-Ping Chen,, “SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD),, 2003
6. Tsung-Hao Chen, Clement Luk, Hyungsuk Kim, and Charlie Chung-Ping Chen,, “INDUCTWISE: Inductance-Wise Interconnect Simulator and Extractor,” IEEE/ACM Design Automation Conference (DAC), 2002
7. Yahong Cao, Yu-Min Lee, Tsung-Hao Chen, and Charlie Chung-Ping Chen,, “HiPRIME: Hierarchical and Passivity Reserved Interconnect Macromodeling Engine for RLKC Power Delivery,” IEEE/ACM Design Automation Conference (DAC),, 2002
8. Ting-Yuan Wang and Charlie Chung-Ping Chen,, “Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm,” 3rd International Symposium on Quality Electronic Design (ISQED), 2002
9. Yu-Min Lee and Charlie Chung-Ping Chen, ", “Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit Method,” IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2001
10. Saisanthosh Balakrishnan, Jong Hyuk Park, Hyungsuk Kim, Yu-Min Lee and Charlie Chung-Ping Chen,, “Linear Time Hierarchical Capacitance Extraction Without Multipole Expansion,” " International Conference on Computer Design (ICCD), 2001
11. Pradeepsunder Ganesh and Charlie Chung-Ping Chen, “RC-in RC-out Model Order Reduction Accurate Up to Second Order Moments,” International Conference on Computer Design (ICCD), 2001
12. Tsung-Hao Chen and Charlie Chung-Ping Chen,, “Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods,” IEEE/ACM Design Automation Conference (DAC),, 2001
Ting-Yuan Wang and Charlie Chung-Ping Chen, “Thermal-ADI: A Linear-Time Chip-Level Dynamic Thermal Simulation Algorithm Based on Alternating-Direction-Implicit (ADI) Method,” ACM International Symposium on Physical Design (ISPD), 2001
14. Yu-Min Lee, Hing Yin Lai, and Charlie Chung-Ping Chen,, “Optimal spacing and capacitance padding for general clock structures,” Asian and South Pacific Design Automation Conference (ASP-DAC),, 2001
15. Yu-min Lee and Charlie Chung-Ping Chen,, “Hierarchical model order reduction for signal-integrity driven interconnect synthesis,” Great Lakes Symposium on VLSI (GLSVLSI), 2001
16. Charlie Chung-Ping Chen, Narayanan Murugesan, Tae-Woo Lee, and Susan C. Hagness, “FDTD-ADI: An Unconditionally Stable Full Wave Maxwell Equation Solver for VLSI Modeling,” " IEEE/ACM International Conference on Computer Aided Design (ICCAD),, 2000
17. Chung-Ping Chen and N. Menezes,, “Noise-Aware Repeater Insertion and Wire-Sizing for On-chip Interconnect Using Hierarchical Moment-Matching,” IEEE/ACM Design Automation Conference (DAC),, 1999
18. Chung-Ping Chen and D.F. Wong, ", “Error-bounded Pade Approximation via Bilinear Conformal Transformation,” IEEE/ACM Design Automation Conference (DAC), 1999
19. N. Menezes and Chung-Ping Chen, “Spec-based Repeater Insertion and Wire-Sizing for On-chip Interconnect,” Twelfth International Conference on VLSI Design,, 1999