Y.C. Lu, J.-K. Huang, K.-Y. Chao, L.-L. Li, and V. P.-H. Hu, “Performance Projection of Si- and 2D Material based SRAM Circuit Ranging From 16 nm to 1 nm Nodes,” Nature Nanotechnology, 1066-1072, Jun. 2024
C.-H. Wu, J. Liu, X.-T. Zheng, H.-F. Chuang, Y.-M. Tseng, M. Kobayashi, C.-J. Su, and V. P.-H. Hu, “Innovative Recovery Strategy for MFIS-FeFETs at Optimal Timing with Robust Endurance: Fast-Unipolar Pulsing (100 ns), Nearly Zero Memory Window Loss (0.02 %), and Self-Tracking Circuit Design,” IEEE Transactions on Electron Devices, vol. 71, no. 5, 3371-3376, May 2024
M. Gupta and V. P.-H. Hu, “Improved Scalability of Negative Capacitance Junctionless Transistors with Underlap Design,” IEEE Transactions on Electron Devices, vol. 70, no. 8, 4043-4048, Aug. 2023
C.-Y. Liao, C.-Y. Lin, Z.-X. Lee, K.-Y. Hsiang, Z.-F. Lou, V. P.-H. Hu, and M. H. Lee, “Mechanisms of Instability Retention for Ferroelectric Field Effect Transistors with HfZrO2 Gate Stack Scaling Down,” Appl. Phys. Lett., vol. 121, Dec. 2022
C.-J. Liu, Y. Wan, L.-J. Li, C.-P. Lin, T.-H. Hou, Z.-Y. Huang, and V. P.-H. Hu, “2D Materials-Based Static Random-Access Memory,” Advanced Materials, Dec. 2022
Sawabe, Y.; Saraya, T.; Hiramoto, T.; Su, C.-J.; Hu, V.P.-H.; Kobayashi, M., “On the Thickness Dependence of the Polarization Switching Kinetics in HfO2-Based Ferroelectric,” Appl. Phys. Lett., Aug. 2022
F. Mo, J. Xiang, X. Mei, Y. Sawabe, T. Saraya, T. Hiramoto, C.-J. Su, V. P.-H. Hu, and M. Kobayashi, “Efficient Erase Operation by GIDL Current for 3D structure FeFET with Gate Stack Engineering and Compact Long-term Retention Model,” IEEE Journal of the Electron Devices Society, vol. 10, , pp. 115-122, Feb. 2022
C.-J. Liu, Y. Wan, L.-J. Li, C.-P. Lin, T.-H. Hou, Z.-Y. Huang, and V. P.-H. Hu, “Two-Dimensional Materials-Based Static Random-Access Memory,” Advanced Materials, 202107894, Dec. 2021
M. Gupta and V. P.-H. Hu, “Influence of Channel Doping on Junctionless and Negative Capacitance Junctionless Transistors,” ECS J. Solid State Sci. Technol., Oct. 2021
M. Gupta and V. P.-H. Hu, “Sensitivity Analysis and Design of Negative Capacitance Junctionless Transistor for High Performance Applications,” IEEE Transactions on Electron Devices, vol. 68, no. 8, pp. 4136-4143, Aug. 2021
V. P.-H. Hu, C.-W. Su, Y.-W. Lee, T.-Y. Ho, C.-C. Cheng, T.-C. Chen, T. Y.-T. Hung, J.-F. Li, Y.-G. Chen, and L.-J. Li, “Energy-Efficient Monolithic 3-D SRAM Cell with BEOL MoS2 FETs for SoC Scaling,” IEEE Transactions on Electron Devices, vol. 67, no. 10, 4216-4221, Oct. 2020
V. P.-H. Hu, H.-H. Lin, Y.-K. Lin, and C. Hu, “Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET),” IEEE Transactions on Electron Devices, 67, 2593-2599, Jun. 2020
M. Gupta and V. P.-H. Hu, “Negative Capacitance Junctionless Device With Mid-Gap Work Function for Low Power Applications,” IEEE Electron Device Letters, 41, 473-476, Mar. 2020
V. P.-H. Hu, P.-C. Chiu, and Y.-C. Lu, “Impact of Work Function Variation, Line-Edge Roughness, and Ferroelectric Properties Variation on Negative Capacitance FETs,” IEEE Journal of the Electron Devices Society, 7, 295-302, 2019
V. P.-H. Hu and C.-T. Wang, “Optimization of III–V heterojunction tunnel FET with non-uniform channel thickness for performance enhancement and ambipolar leakage suppression,” Japanese Journal of Applied Physics, 57, 04FD18-undefined, Mar. 2018
V. P.-H. Hu and P.-C. Chiu, “Analysis of switching characteristics for negative capacitance ultra-thin-body germanium-on-insulator MOSFETs,” Japanese Journal of Applied Physics, 57, 04FD02-undefined, Feb. 2018
V. P.-H. Hu, “Reliability-Tolerant Design for Ultra-Thin-Body GeOI 6T SRAM Cell and Sense Amplifier,” IEEE Journal of the Electron Devices Society, 5, 107-111, Mar. 2017
C.-H. Yu, M.-L. Fan, K.-C. Yu, V. P.-H. Hu, Pin Su and C.-T. Chuang, “Evaluation of Monolayer and Bilayer 2-D Transition Metal Dichalcogenide Devices for SRAM Applications,” IEEE Transactions on Electron Devices, 63, 625-630, Feb. 2016
V. P.-H. Hu, M.-L. Fan, P. Su and C.-T. Chuang, “Analysis of GeOI FinFET 6T SRAM Cells With Variation-Tolerant WLUD Read-Assist and TVC Write-Assist,” IEEE Transactions on Electron Devices, 62, 1710-1715, Jun. 2015
C.-W. Hsu, M.-L. Fan, V. P.-H. Hu, and Pin Su, “Investigation and Simulation of Work-Function Variation for III–V Broken-Gap Heterojunction Tunnel FET,” IEEE Journal of the Electron Devices Society, 3, 194-199, May 2015
Y.-N. Chen, C.-J. Chen, M.-L. Fan, V. P.-H. Hu, Pin Su and C.-T. Chuang, “Impacts of Work Function Variation and Line-Edge Roughness on TFET and FinFET Devices and 32-Bit CLA Circuits,” Journal of Low Power Electronics and Applications, 5, 101-115, May 2015
M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, C.-W. Hsu, Pin Su and C.-T. Chuang, “Investigation of Backgate-Biasing Effect for Ultrathin-Body III-V Heterojunction Tunnel FET,” IEEE Transactions on Electron Devices, 62, 107-113, Jan. 2015
Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, Pin Su and C.-T. Chuang, “Evaluation of Stability, Performance of Ultra-Low Voltage MOSFET, TFET, and Mixed TFET-MOSFET SRAM Cell With Write-Assist Circuits,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 4, 389-399, Dec. 2014
Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, Pin Su and C.-T. Chuang, “Evaluation of Sub-0.2 V High-Speed Low-Power Circuits Using Hetero-Channel MOSFET and Tunneling FET Devices,” IEEE Transactions on Circuits and Systems I: Regular Papers, 61, 3339-3347, Dec. 2014
M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su and C.-T. Chuang, “Stability and Performance Optimization of Heterochannel Monolithic 3-D SRAM Cells Considering Interlayer Coupling,” IEEE Transactions on Electron Devices, 61, 3448-3455, Oct. 2014
M.-L. Fan, S.-Y. Yang, V. P.-H. Hu, Y.-N. Chen, P. Su and C.-T. Chuang, “Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits,” Microelectronics Reliability, 54, 698-711, Apr. 2014
V. P.-H. Hu, M.-L. Fan, P. Su and C.-T. Chuang, “Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET,” IEEE Transactions on Electron Devices, 60, 3596-3600, Oct. 2013
V. P.-H. Hu, M.-L. Fan, P. Su and C.-T. Chuang, “Threshold Voltage Design of UTB SOI SRAM With Improved Stability/Variability for Ultralow Voltage Near Subthreshold Operation,” IEEE Transactions on Nanotechnology, 12, 524-531, Jul. 2013
M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su and C.-T. Chuang, “Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET,” IEEE Transactions on Electron Devices, 60, 2038-2044, Jun. 2013
Y.-N. Chen, M.-L. Fan, V. P.-H. Hu, P. Su and C.-T. Chuang, “Design and Analysis of Robust Tunneling FET SRAM,” IEEE Transactions on Electron Devices, 60, 1092-1098, Mar. 2013
V. P.-H. Hu, M.-L. Fan, P. Su and C.-T. Chuang, “Threshold Voltage Design and Performance Assessment of Hetero-Channel SRAM Cells,” IEEE Transactions on Electron Devices, 60, 147-152, Jan. 2013
M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su and C.-T. Chuang, “Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications,” IEEE Transactions on Circuits and Systems II: Express Briefs, 59, 878-882, Dec. 2012
M.-L. Fan, V. P.-H. Hu, Y.-N. Chen, P. Su and C.-T. Chuang, “Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits,” IEEE Transactions on Electron Devices, 59, 2227-2234, Aug. 2012
C.-H. Yu, Y.-S. Wu, V. P.-H. Hu, and P. Su, “Impact of Quantum Confinement on Backgate-Bias Modulated Threshold-Voltage and Subthreshold Characteristics for Ultra-Thin-Body GeOI MOSFETs,” IEEE Transactions on Electron Devices, 59, 1851-1855, Jul. 2012
C.-Y. Hsieh, M.-L. Fan, V. P.-H. Hu, “Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 20, 1201-1210, Jul. 2012
C.-H. Yu, Y.-S. Wu, V. P.-H. Hu, and P. Su, “Impact of Quantum Confinement on Subthreshold Swing and Electrostatic Integrity of Ultra-Thin-Body GeOI and InGaAs-OI n-MOSFETs,” IEEE Transactions on Nanotechnology, 11, 287-291, Mar. 2012
V. P.-H. Hu, M.-L. Fan, P. Su and C.-T. Chuang, “Band-to-Band-Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs Using Transistor Stacking,” IEEE Electron Device Letters, 33, 197-199, Feb. 2012
V. P.-H. Hu, M.-L. Fan, P. Su and C.-T. Chuang, “Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity,” IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 1, 335-342, Sept. 2011
V. P.-H. Hu, M.-L. Fan, C.-Y. Hsieh, P. Su and C.-T. Chuang, “FinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI, Surface Orientation and Various Gate Dielectrics,” IEEE Transactions on Electron Devices, 58, 805-811, Mar. 2011
V. P.-H. Hu, Y.-S. Wu, and P. Su, “Investigation of Electrostatic Integrity for Ultrathin-Body Germanium-On-Nothing MOSFET,” IEEE Transactions on Nanotechnology, 10, 325-330, Mar. 2011
V. P.-H. Hu, Y.-S. Wu, M.-L. Fan, P. Su and C.-T. Chuang, “Static Noise Margin of Ultrathin-Body SOI Subthreshold SRAM Cells—An Assessment Based on Analytical Solutions of Poisson's Equation,” IEEE Transactions on Electron Devices, 56, 2120-2127, Sept. 2009
Conference & proceeding papers:
Y.-C. Lu, M.-L. Wu, and V. P.-H. Hu, “Conflict-Free and Area-Efficient 4N4P CFET 8T SRAM with Double-Sided Signal Routing for Multibit Compute-in-Memory in AI Edge Devices,” 2024 IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, Dec. 2024
H.-C. Chiu and V. P.-H. Hu, “Improved RF Performance with Buried Power Rail and Contact over Active Gate in Nanosheet FETs,” IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, May 2024
W.-C. Lee and V. P.-H. Hu, “Enhanced Memory Window for Ferroelectric FinFET on Bulk Substrate through Underlap Design,” International Electron Devices & Materials Symposium & Symposium on Nano-Device Circuits and Technologies (IEDMS & SNDCT), 2024
C.-H. Wu, T.-Y. Lin, C.-Y. Chiu, C.-J. Su, and V. P.-H. Hu, “Enhancing Annealing Strategies for Back-End-of-Line-Compatible HfO2-Based Ferroelectric Capacitors with Time Periods and Gas Species,” IEEE Silicon Nanoelectronics Workshop (SNW), 2024
C.-H. Wu, T.-Y. Lin, C.-J. Su, and V. P.-H. Hu, “Comparative Studies of Thermal Stability Between Back-End-of-Line Superlattice and Solid Solution Hf0.5Zr0.5O2 Ferroelectric Memories on Ferroelectricity and Switching Dynamics,” International Conference on Solid State Devices and Materials (SSDM), 2024
C.-H. Wu, J. Liu, X.-T. Zheng, Y.-M. Tseng, M. Kobayashi, V. P.-H. Hu, and C.-J. Su, “Robust Recovery Scheme for MFIS-FeFETs at Optimal Timing with Prolonged Endurance: Fast-Unipolar Pulsing (100 ns), Nearly Zero Memory Window Loss (0.02 %), and Self-Tracking Circuit Design,” 2023 IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, Dec. 2023
J. Liu, C.-H. Wu, M. Kobayashi, C.-J. Su, and V. P.-H. Hu, “Comparative Study of Variability in FeFET Memories with Different Erase Voltages,” International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, Sept. 2023
C.-H. Wu, C.-J. Su, and V. P.-H. Hu, “Switching Characteristics and Endurance Analysis of Nanolaminated Ferroelectric HZO Gate Stack with Al2O3 for Back-End-of-Line Applications,” International Conference on Solid State Devices and Materials (SSDM), Nagoya, Japan, Sept. 2023
X.-T. Zheng and V. P.-H. Hu, “Improved Radiation Hardness for Nanosheet FETs with Partial Bottom Dielectric Isolation,” IEEE Silicon Nanoelectronics Workshop (SNW), Kyoto, Japan, Jun. 2023
J. Liu, C.-H. Wu, C.-J. Su, and V. P.-H. Hu, “Variability Analysis of FeFETs considering Different Erase Voltages,” The 3rd Symposium on Nano-Device Circuits and Technologies (SNDCT), Hsinchu, Taiwan, May 2023
Y.-C. Lu, M. Lee, Z.-Y. Huang and V. P.-H. Hu, “Analysis of Monolithic 3D SRAM with Back-End-of-Line-compatible Transistors,” 2023 International VLSI Symposium on Technology, Systems and Applications (VLSI TSA), Hsinchu, Taiwan, Apr. 2023
H.-F. Chuang and V. P.-H. Hu, “Variation-Tolerant Ferroelectric FET-based Ternary Content-Addressable Memories (TCAM) Cell for Meta-learning Application,” IEEE Electron Devices Technology and Manufacturing (EDTM), Seoul, Korea, Mar. 2023
S.-F. Fang and V. P.-H. Hu, “Stability and Performance Optimization of 6T SRAM Cell at Cryogenic Temperature,” IEEE Electron Devices Technology and Manufacturing (EDTM), Seoul, Korea, Mar. 2023
Y.-M. Pan, C.-K. Lu, and V. P.-H. Hu, “Linearity Analysis of FeFET Synaptic Devices considering Random Phase Distributions,” IEEE Electron Devices Technology and Manufacturing (EDTM), Seoul, Korea, Mar. 2023
M. Lee, Z.-Y. Huang, S.-F. Fang, Y.-C. Lu, and V. P.-H. Hu, “Energy- and Area-Efficient 8T SRAM Cell with FEOL CFETs and BEOL-Compatible Transistors,” 2022 IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, Dec. 2022
M. Gupta and V. P.-H. Hu, “Sensitivity Analysis of Ferroelectric Junctionless Transistors for Non-volatile Memory Applications,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 2022
A.-F. Li, R.-Y. Huang, and V. P.-H. Hu, “Variation-Tolerant Recall Operation for Nonvolatile SRAM Integrated with Ferroelectric Capacitor,” IEEE Electron Devices Technology and Manufacturing (EDTM), Oita, Japan, Mar. 2022
V. P.-H. Hu, C.-J. Liu, H.-L. Chiang, J.-F. Wang, C.-C. Cheng, T.-C. Chen, and M.-F. Chang, “High-Density and High-Speed 4T FinFET SRAM for Cryogenic Computing,” IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, Dec. 2021
Wen Tsen Fu, Chun-Jung Su, and V. P.-H. Hu, “Effects of Measurement Schemes on Junctionless Ferroelectric FETs,” International Electron Devices & Materials Symposium, Taiwan, Nov. 2021
Chun-Chi Yu and V. P.-H. Hu, “Analysis and Design of FeMFET Non-volatile Memory for Low Voltage Operation,” International Electron Devices & Materials Symposium, Taiwan, Nov. 2021
Cheng-Wei Liang and V. P.-H. Hu, “Analysis of Work Function and Ferroelectric Variations for FeFET Nonvolatile Memory,” International Electron Devices & Materials Symp., Taiwan, Nov. 2021
Ai-Fang Li and V. P.-H. Hu, “Variation-Tolerant Recall Operation for Nonvolatile SRAM Integrated with Ferroelectric Capacitor,” International Electron Devices & Materials Symp., Taiwan, Nov. 2021
M. Gupta and V. P.-H. Hu, “Optimization of Junctionless Ferroelectric Field-Effect Transistors for Non-Volatile Memory Applications,” International Conference on Solid State Devices and Materials (SSDM), Japan, Sept. 2021
V. P.-H. Hu and C.-J. Liu, “Static Noise Margin Analysis for Cryo-CMOS SRAM Cell,” IEEE International Symposium on Radio-Frequency Integration Technology (RFIT2021), Taiwan, Aug. 2021
F. Mo, J. Xiang, X. Mei, Y. Sawabe, T. Saraya, T. Hiramoto, C.-J. Su, V. P.-H. Hu, and M. Kobayashi, “Critical Role of GIDL Current for Erase Operation in 3D Vertical FeFET and Compact Long-term FeFET Retention Model,” Symposia on VLSI Technology & Circuits (VLSI), Kyoto, Japan, Jun. 2021
V. P.-H. Hu, Cheng-Wei Su, Chun-Chi Yu, Chang-Ju Liu, and Cheng-Yang Weng, “Monolithic 3D SRAM Cell with Stacked Two-Dimensional Materials Based FETs at 2nm Node,” IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, May 2021
M. Gupta and V. P.-H. Hu, “Improved Switching Time in Negative Capacitance Junctionless Transistors,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 2021
C. J. Su, M. K. Huang, K. S. Lee, V. P.-H. Hu et al., “3D Integration of Vertical-Stacking of MoS2 and Si CMOS Featuring Embedded 2T 1R Configuration Demonstrated on Full Wafer,” International Electron Devices Meeting (IEDM), Dec. 2020
M. Gupta and V. P.-H. Hu, “Influence of Channel Doping on Junctionless and Negative Capacitance Junctionless Transistors,” International Electron Devices & Materials Symposium, Taoyuan, Taiwan, Oct. 2020
Y.-W. Lee and V. P.-H. Hu, “Improved Energy Efficiency for Ferroelectric FET Non-volatile Memory using Split-gate Design,” IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, May 2020
M. Gupta and V. P.-H. Hu, “Subthreshold Behavior of Ferroelectric Junctionless Transistor,” International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 2020
V. P.-H. Hu, H.-H. Lin, Z.-A. Zheng, Z.-T. Lin, Y.-C. Lu, T.-Y. Ho, Y.-W. Lee, C.-W. Su, and C.-J. Su, “Split-Gate FeFET (SG-FeFET) with Dynamic Memory Window Modulation for Non-Volatile Memory and Neuromorphic Applications,” Symposia on VLSI Technology & Circuits (VLSI), Kyoto, Japan
V. P.-H. Hu, P.-C. Chiu, A. B. Sachid, and C. Hu, “Negative capacitance enables FinFET and FDSOI scaling to 2 nm node,” 2017 IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA
Z.-A. Zheng and V. P.-H. Hu, “Improved Read Stability and Writability of Negative Capacitance FinFET SRAM Cell for Subthreshold Operation,” 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan
H.-H. Lin and V. P.-H. Hu, “Device Designs and Analog Performance Analysis for Negative-Capacitance Vertical-Tunnel FET,” 2019 20th International Symposium on Quality Electronic Design (ISQED), Santa Clara, CA, USA
P.-C. Chiu and V. P.-H. Hu, “Analysis of Negative Capacitance UTB SOI MOSFETs considering Line-Edge Roughness and Work Function Variation,” 2018 IEEE 2nd Electron Devices Technology and Manufacturing Conference (EDTM), Kobe