張耀文特聘教授的著作列表 - Publication List of Yao-Wen Chang

Publication List of 張耀文 Yao-Wen Chang

Journal articles & book chapters:

  1. Y.-W. Chang, “Please see http://cc.ee.ntu.edu.tw/~ywchang/publications.html,” for his journal publication list, 2016
  2. H.-Y. Chang, H.-R. Jiang, and Y.-W. Chang, “Timing ECO optimization via Bezier curve smoothing and fixability identification,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 12, pp. 1857--1866, Dec. 2012
  3. K.-H. Ho, J.-H. Jiang, and Y.-W. Chang, “TRECO: Dynamic technology remapping for timing engineering change orders,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 11, pp. 1723--1733, Nov. 2012
  4. M.-K. Hsu and Y.-W. Chang, “Unified analytical global placement for large-scale mixed-size circuit designs,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 9, pp. 1366-1378, Sept. 2012
  5. X.-W. Shih and Y.-W. Chang, “Fast timing-model independent buffered clock-tree synthesis,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 9, pp. 1393-1404, Sept. 2012
  6. C.-W. Lin, P.-W. Lee, Y.-W. Chang, C.-F. Shen, and W.-C. Tseng, “An efficient pre-assignment routing algorithm for flip-chip designs,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 6, pp. 878--889, Jun. 2012
  7. S.-Y. Fang, S.-Y. Chen, and Y.-W. Chang, “Native-conflict-aware wire perturbation for double patterning technology,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 5, pp. 703-716, Mar. 2012
  8. Y.-L. Chuang, P.-W. Lee, and Y.-W. Chang, “Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 30, No. 12, pp. 1856--1869, Dec. 2011
  9. Y.-L. Chuang, S. Kim, Y. Shin, and Y.-W. Chang, “Pulsed-latch aware placement for timing-integrity optimization,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 30, No. 11, pp. 1649 - 1662, Nov. 2011
  10. C.-Y. Lin and Y.-W. Chang, “Cross-contamination aware design methodology for pin-constrained digital microfluidic biochips,” Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 30, No. 6, pp. 817--828, Jun. 2011
  11. M. P.-H. Lin, H. Zhang, M. D. F. Wong, and Y.-W. Chang, “Thermal-driven analog placement considering device matching,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 30, No. 3, pp. 325--336, Mar. 2011
  12. C.-H. Hsu, Y.-W. Chang, and S. R. Nassif, “Simultaneous layout migration and decomposition for double patterning technology,” EEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 30, No. 9, pp. 284--294, Feb. 2011
  13. J.-W. Fang and Y.-W. Chang, “Area-I/O flip-chip routing for chip-package co-design considering signal skews,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 29, No. 5, pp. 711—721, May 2010
  14. C.-H. Hsu, H.-Y. Chen, and Y.-W. Chang, “Multi-layer global routing with via and wire capacity considerations,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 29, No. 5, pp. 685 – 696, May 2010
  15. K.-H. Ho, Y.-P. chen, J.-W. Fang, and Y.-W. Chang, “ECO timing optimization using spare cells and technology remapping,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 29, No. 5, pp. 697--710, May 2010
  16. T.-C. Chen, G.-W. Liao, and Y.-W. Chang, “Predictive formulae for OPC with applications to lithography-friendly routing,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 29, No. 1, pp. 40—50, Jan. 2010
  17. C.-Y. Lin and Y.-W. Chang, “ILP-based pin-count aware design methodology for microfluidic biochips,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2010
  18. P.-H. Yu, S. Sapatnekar, C.-L. Yang, and Y.-W. Chang, “A progressive-ILP based routing algorithm for cross-referencing biochips,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 28, No. 9, pp. 1295--1306, Sept. 2009
  19. H.-Y. Chen and Y.-W. Chang, “Routing for manufacturability and reliability (Invited Feature Paper),” IEEE Circuits and Systems Magazine, pp. 20--31, Sept. 2009
  20. Y.-W. Chang, Z.-W. Jiang, and T.-C. Chen, “Essential issues in analytical placement algorithms (invited keynote paper),” IPSJ Transactions on System LSI Design Methodology, Vol. 2, pp. 145--166, Aug. 2009
  21. P.-H. Lin, Y.-W. Chang, and S.-C. Lin, “Analog placement based on symmetry-island and tree formulation,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 28, No. 6, pp. 791--804, Jun. 2009
  22. W.-P. Lee, H.-Y. Liu, and Y.-W. Chang, “Voltage island partitioning and floorplanning under timing constraints,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 28, No. 5, pp. 690--702, May 2009
  23. H.-Y. Chen, S.-J. Chou, S.-L. Wang, and Y.-W. Chang, “A novel wire-density-driven full-chip routing system for CMP variation control,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 28, No. 2, pp. 193--206, Feb. 2009
  24. J.-W. Fang, C.-H. Hsu, and Y.-W. Chang, “An integer linear programming based routing algorithm for flip-chip designs,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 28, No. 1, pp. 98--110, Jan. 2009
  25. P.-H. Yu, C.-L. Yang, and Y.-W. Chang, “T-trees: A Tree-Based Representation for Temporal Floorplanning,” ACM Trans. Design Automation of Electronic Systems, 2009
  26. T.-C. Chen, M. Cho, D. Z. Pan, and Y.-W. Chang, “Metal-density driven placement for CMP variation and routability,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 12, pp. 2145--2155, Dec. 2008
  27. C.-W. Lin, S.-L. Huang, K.-C. Hsu, M.-X. Li, and Y.-W. Chang, “Multi-layer obstacle-avoiding rectilinear Steiner tree construction based on spanning graphs,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 11, pp. 2007--2016, Nov. 2008
  28. P.-H. Yu, C.-L. Yang, and Y.-W. Chang, “BioRoute: a network-flow based routing algorithm for the synthesis of digital microfluidic biochips,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 11, pp. 1928--1941, Nov. 2008
  29. T.-C. Chen, P.-H. Yuh, Y.-W. Chang, F.-J. Huang, and D. Liu, “ MP-trees: A packing-based macro placement algorithm for modern mixed-size designs,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 9, pp. 1621--1634, Sept. 2008
  30. C.-H. Liu, H.-Y. Liu, C.-W. Lin, S.-J. Chou, Y.-W. Chang, S.-Y. Kuo, and S.-Y. Yuan, “An efficient graph-based algorithm for ESD current path analysis,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 8, pp. 1363--1375, Aug. 2008
  31. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, “NTUplace3: an analytical placer for large-scale mixed-size designs with preplaced blocks and density constraints,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 7, pp. 1228--1240, Jul. 2008
  32. Z.-W. Jiang and Y.-W. Chang, “An optimal network-flow-based simultaneous diode and jumper insertion algorithm for antenna fixing,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 6, pp. 1055--1065, Jun. 2008
  33. H.-Y. Chen, M.-F. Chiang, Y.-W. Chang, L. Chen, and B. Han, “Full-chip routing considering double-via insertion,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 5, pp. 844--857, May 2008
  34. C.-W. Lin, S.-Y. Chen, C.-F. Li, Y.-W. Chang, and C.-L. Yang, “Obstacle-avoiding rectilinear Steiner tree construction based on spanning graphs,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems. (TCAD), Vol. 27, No. 4, Apr. 2008
  35. T.-C. Chen, Y.-L. Chuang, and Y.-W. Chang, “Effective wire models for X-architecture placement,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 4, Apr. 2008
  36. T.-C. Chen, Y.-W. Chang, and S.-C. Lin, “A new multilevel framework for large-scale interconnect-driven floorplanning,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 27, No. 2, Feb. 2008
  37. P.-H. Yu, C.-L. Yang, and Y.-W. Chang, “Placement of defect-tolerant digital microfluidic biochips using the T-tree formulation,” ACM Journal of Emerging Technologies in Computing Systems (JETC), Vol. 3, No. 3, 32 pages, Nov. 2007
  38. B.-Y. Su and Y.-W. Chang, “An exact jumper insertion algorithm for antenna avoidance/fixing,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 10, pp. 1818--1829, Oct. 2007
  39. P.-H. Yu, C.-L. Yang, and Y.-W. Chang, “Temporal floorplanning using the three-dimensional transitive closure sub-graph,” ACM Trans. Design Automation of Electronic Systems, Vol. 12, No. 4, 34 pages, Sept. 2007
  40. K. S.-M. Li, Y.-W. Chang, C.-L. Lee, C.-C. Su, and J. E Chen,, “Multilevel full-chip routing with testability and yield enhancement,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 9, pp. 1625--1636, Sept. 2007
  41. J.-W. Fang, I.-J. Lin, Y.-W. Chang, and J.-H. Wang,, “A network-flow based RDL routing algorithm for flip chip design,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 8, pp. 1417--1429, Aug. 2007
  42. H.-C. Lee, Y.-W. Chang, and H. Yang, “MB*-tree: A multilevel floorplanner for large-scale building-module design,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 8, pp. 1430--1444, Aug. 2007
  43. T.-C. Chen and Y.-W. Chang, “Multilevel full-chip gridless routing with applications to optical proximity correction,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 26, No. 6, pp. 1041--1053, Jun. 2007
  44. B.-Y. Su, Y.-W. Chang, and J. Hu, “An exact jumper insertion algorithm for antenna violation avoidance/fixing considering routing obstacles,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 4, 719--734, Apr. 2007
  45. C.-W. Liu and Y.-W. Chang, “Power/ground network and floorplan co-synthesis for fast design convergence,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, Vol. 27, No. 4, pp. 693—704, Apr. 2007
  46. K. S.-M. Li, C.-C. Su, Y.-W. Chang, C.-L. Lee, and J. E Chen, “P1500 Standard Compatible Interconnect Diagnosis for Delay and Crosstalk Faults,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 11, 2513--2525, Nov. 2006
  47. S.-W. Tu, J.-Y. Jou, and Y.-W. Chang, “RLC coupling-aware simulation and on-chip bus encoding for delay reduction,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 10, 2258—2264, Oct. 2006
  48. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, “Multilevel Routing with Jumper Insertion for Antenna Avoidance,” Integration: The VLSI Journal, Vol. 39, Issue 4, pp. 420--432, Jul. 2006
  49. T.-C. Chen and Y.-W. Chang, “Modern Floorplanning Based on B*-trees and Fast Simulated Annealing,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, No. 4, 637—650, Apr. 2006
  50. H.-R. Jiang, S.-R., Pan, Y.-W. Chang, and J.-Y. Jou,, “Reliable crosstalk-driven interconnect optimization,” ACM Trans. on Design Automation of Electronic Systems (TODAES),, Vol. 11, No. 1, 88—103, Jan. 2006
  51. T.-Y. Ho, Y.-W. Chang, S.-J. Chen, and D. T. Lee, “Multilevel full-chip routing considering crosstalk and performance,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 24, No. 6, pp. 869--878, Jun. 2005
  52. J.-M. Lin and Y.-W. Chang, “TCG: A transitive closure graph based representation for general floorplans,” IEEE Transactions on VLSI Systems, Vol. 13, No. 4, 288--292, Apr. 2005
  53. G.-M. Wu, C.-T. M. Chao, and Y.-W. Chang,, “A clustering and probability based partitioning algorithm for time-multiplexed FPGAs,” Integration: The VLSI Journal., Vol. 38, Issue 2, pp. 245—265, Dec. 2004
  54. J.-M. Lin and Y.-W. Chang, “TCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 23, No. 6, 968—980, Jul. 2004
  55. Y.-W. Chang and S.-P. Lin, “MR: A New Framework for Multilevel Full-Chip Routing,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 23, No. 5, 793—800, May 2004
  56. H.-R. Jiang, Y.-W. Chang, J.-Y. Jou, K.-Y. Chao, “Simultaneous floorplanning and buffer block planning,” IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 23, No. 5, 694—703, May 2004
  57. G.-M. Wu, M. Shyu, and Y.-W. Chang, “Universal switch blocks for three-dimensional FPGA design,” IEE Proceedings---Circuits, Devices, and Systems, Vol. 151, No. 1, 49—57, Feb. 2004
  58. T.-C. Chen, S.-R. Pan, and Y.-W. Chang, “Timing modeling and optimization under the transmission line model,” IEEE Transactions on VLSI Systems, Vol. 12, No. 1, pp. 28--41, Jan. 2004
  59. J.-M. Lin, Y.-W. Chang, and S.-P. Lin,, “Corner sequence: A P-admissible floorplan representation with a worst-case linear-time packing scheme,” IEEE Transactions on VLSI Systems (TVLSI),, Vol. 11, No. 4,, pp. 679--686,, Aug. 2003
  60. G.-M. Wu, Y.-C. Chang, and Y.-W. Chang,, “Rectilinear block placement using B*-trees,” ACM Trans. on Design Automation of Electronic Systems (TODAES),, Vol. 8., No. 2,, pp. 188-202,, Apr. 2003
  61. S.-W. Tu, W.-Z. Shen, Y.-W. Chang, T.-C. Chen, and J.-Y. Jou,, “Inductance modeling for on-chip interconnects,” Analog Integrated Circuits and Signal Processing Journal,, Vol. 35, No 1,, pp. 65-78,, Apr. 2003
  62. Y.-W. Chang, K. Zhu, G.-M. Wu, D. F. Wong, G.-M. Wu, and C. K. Wong,, “Analysis of FPGA/FPIC switch modules,” ACM Trans. on Design Automation of Electronic Systems (TODAES),, Vol. 8, No. 1,, pp. 11-37, Jan. 2003
  63. J.-M. Lin, H.-L. Lin, and Y.-W. Chang,, “Arbitrarily shaped rectilinear module packing using TCG,” IEEE Trans. on VLSI Systems (TVLSI),, Vol. 10, No. 6,, pp. 886-901,, Dec. 2002
  64. Y.-M. Lee, C.-P. Chen, Y.-W. Chang, and D.-F. Wong,, “Simultaneous buffer-sizing and wire-sizing for clock trees based on Lagrangian relaxation,” VLSI Design,, Vol. 15, No. 3,, pp. 587--594,, Nov. 2002
  65. G.-M. Wu, J.-M. Lin, and Y.-W. Chang,, “Performance-driven placement for dynamically reconfigurable FPGAs,” ACM Trans. on Design Automation of Electronic Systems (TODAES),, Vol. 7, No. 4,, pp. 628-642,, Oct. 2002
  66. J.-M. Lin, H.-E. Yi, and Y.-W. Chang, “Module placement with boundary constraints using B*-trees,” IEE Proceedings--Circuits, Devices and Systems,, Vol. 149, No. 4,, pp. 251--256,, Aug. 2002
  67. H. Fang, Y.-L. Wu, and Y.-W. Chang,, “Comments on “Generic universal switch blocks,” IEEE Trans. on Computers (TC),, Vol. 51, No. 1,, pp. 93—95,, 2002
  68. G.-M. Wu, J.-M. Lin, and Y.-W. Chang,, “Generic ILP-based approaches for time-multiplexed FPGA partitioning,” IEEE Trans. on Computer-Aided Design (TCAD),, Vol. 20, No. 10,, pp. 1266—1274,, Oct. 2001
  69. Y.-W. Chang, J.-M. Lin, and D. F. Wong,, “A matching-based algorithm for FPGA channel segmentation design,” IEEE Trans. on Computer-Aided Design (TCAD),, Vol. 20, No. 6,, pp. 784-791,, Jun. 2001
  70. H.-R. Jiang, Y.-W. Chang, and J.-Y. Jou,, “Crosstalk-driven interconnect optimization by simultaneous gate and wire sizing,” IEEE Trans. on Computer-Aided Design (TCAD),, Vol. 19, No. 9,, pp. 999--1010,, Sept. 2000
  71. Y.-W. Chang, K. Zhu, and D. F. Wong,, “Timing-driven routing for symmetrical-array-based FPGAs,',” ACM Trans. on Design Automation of Electronic Systems (TODAES),, Vol. 5, No. 3,, pp. 433-450,, Jul. 2000
  72. M. Shyu, Y.-D. Chang, G.-M. Wu, and Y.-W. Chang,, “Generic universal switch blocks,” IEEE Trans. on Computers (TC),, vol. 49, no. 4,, pp. 348-359,, Apr. 2000
  73. G.-M. Wu and Y.-W. Chang, “Quasi-universal switch matrices for FPD design,” IEEE Trans. on Computers (TC), Vol. 48, No. 10,, pp. 1107-1122, Oct. 1999
  74. Y.-W. Chang, “Please see http://cc.ee.ntu.edu.tw/~ywchang,” for my publication list.

Conference & proceeding papers:

  1. Y.-W. Chang, “Please see http://cc.ee.ntu.edu.tw/~ywchang/publications.html,” for his conference publication list, 2016
  2. S.-Y. Fang, I.-J. Liu, and Y.-W. Chang, “Stitch-aware routing framework for multiple e-beam lithography,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2013), Austin, TX, Jun. 2013
  3. H.-C. Chang-Chien, H.-C. Ou, T.-C. Chen, and Y.-W. Chang, “Double patterning lithography-aware analog placement,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2013), Austin, TX, Jun. 2013
  4. H.-C. Ou, K.-H. Ho, Y.-W. Chang, and H.-F. Tsao, “Coupling-aware length-ratio-matching routing for capacitor arrays in analog integrated circuits,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2013), Austin, TX, Jun. 2013
  5. T.-H. Lin, P. Banerjee, and Y.-W. Chang, “An efficient and effective analytical placer for FPGAs,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2013), Austin, TX, Jun. 2013
  6. Y.-K. Ho and Y.-W. Chang, “Multiple chip planning for chip-interposer codesign,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2013), Austin, TX, Jun. 2013
  7. H.-C. Oh, S.-C. Chang-Chien, and Y.-W. Chang, “Simultaneous analog placement and pouting with current flow and current density considerations,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2013), Austin, TX, Jun. 2013
  8. M.-K. Hsu, Y.-F. Chen, C.-C. Huang, T.-C. Chen, and Y.-W. Chang, “Routability-driven placement for hierarchical mixed-size circuit designs,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2013), Austin, TX, Jun. 2013
  9. S.-Y. Fang, C.-W. Lin, G.-W. Liao, and Y.-W. Chang, “Simultaneous OPC- and CMP-aware routing based on accurate closed-form modeling,” to appear in Proceedings of ACM International symposium on Physical Design (ISPD-2013), Stateline, NV, Mar. 2013
  10. Y.-K. Ho, X.-W. Shih, Y.-W. Chang, and C.-K. Cheng, “Layer minimization in escape routing for staggered-pin-array PCBs,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2013), Yokohama, Japan, Jan. 2013
  11. X.-W. Shih, T.-H. Hsu, H.-C. Lee, Y.-W. Chang, and K.-Y. Chao, “Symmetrical buffered clock-tree synthesis with supply-voltage alignment,” in Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2013), Yokohama, Japan, Jan. 2013
  12. S.-Y. Fang, C.-W. Lin, G.-W. Liao, and Y.-W. Chang, “Accurate closed-form modeling for simultaneous OPC- and CMP-aware routing,” in the 23rd VLSI Design/CAD Symposium, Ping-Tong, Taiwan, Aug. 2012
  13. T.-H. Lin, P. Banerjee, and Y.-W. Chang, “An efficient analytical placer for FPGA designs,” in the 23rd VLSI Design/CAD Symposium, Ping-Tong, Taiwan, Aug. 2012
  14. S.-Y. Fang and Y.-W. Chang, “Simultaneous flare level and flare variation minimization with dummification in EUVL,” n Proceedings of ACM/IEEE Design Automation Conference (DAC-2012), San Francisco, CA, Jun. 2012
  15. H.-C. Lee and Y.-W. Chang, “A chip-package-board co-design methodology,” n Proceedings of ACM/IEEE Design Automation Conference (DAC-2012), San Francisco, CA, Jun. 2012
  16. S. Chou, M.-K. Hsu, and Y.-W. Chang, “Structure-aware placement for datapath intensive circuit designs,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2012), San Francisco, CA, Jun. 2012
  17. S.-Y. Fang and Y.-W. Chang, “A novel layout decomposition algorithm for triple patterning lithography,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2012), San Francisco, CA, Jun. 2012
  18. H.-C. Oh, S.-C. Chang-Chien, and Y.-W. Chang, “Non-uniform multilevel analog routing with matching constraints,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2012), San Francisco, CA, Jun. 2012
  19. H.-Y. Chang, H.-R. Jiang, and Y.-W. Chang, “Timing ECO optimization using metal-configurable gate-array spare cells,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2012), San Francisco, CA, Jun. 2012
  20. P.-W. Lee, H.-C. Lee, Y.-K. Ho, Y.-W. Chang, I.-J. Lin, and C. Shen, “Obstacle-avoiding free-assignment routing for flip-chip designs,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2012), San Francisco, CA, Jun. 2012
  21. D.-C. Juan, Y.-L. Chuang, D. Marculescu, and Y.-W. Chang, “Statistical Thermal Modeling and Optimization Considering Leakage Power Variations,” to appear in Proceedings of IEEE/ACM European Design Automation and Test Conference (DATE-2012), Dresden, Germany, Mar. 2012
  22. S.-Y. Fang and Y.-W. Chang, “Graph-based subfield scheduling for electron-beam photomask fabrication,” in Proceedings of ACM International symposium on Physical Design (ISPD-2012), Napa, CA, Mar. 2012
  23. P.-Y. Chou, H.-C. Ou, Y.-W. Chang, “Heterogeneous B*-trees for analog placement with symmetry and regularity considerations,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2011), San Jose, Nov. 2011
  24. H.-Y. Chang, I. H.-R. Jiang, and Y.-W. Chang, “Timing ECO optimization via Bezier curve smoothing and fixability identification,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2011), San Jose, Nov. 2011
  25. Y.-K. Ho, H.-C. Lee, and Y.-W. Chang, “Escape routing for staggered-pin-array PCBs,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2011), San Jose, Nov. 2011
  26. H.-F. Tsao, P.-Y. Chou, S.-L. Huang, Y.-W. Chang, M. P.-H. Lin, D.-P. Chen, and D. Liu, “A corner stitching compliant B*-tree representation and its applications to analog placement,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2011), San Jose, Nov. 2011
  27. Y.-L. Chuang, H.-T. Lin, T.-Y. Ho, Y.-W. Chang, and D. Marculescu, “PRICE: Power reduction by placement and clock-network co-synthesis for pulsed-latch designs,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2011), San Jose, Nov. 2011
  28. M.-K. Hsu, S. Chou, T.-H. Lin, and Y.-W. Chang, “A novel routability-driven analytical placement algorithm for large-scale mixed-size circuit designs,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2011), San Jose, Nov. 2011
  29. M.-K. Hau, S. chou, T.-H. Lin, and Y.-W. Chang, “A novel routability-driven analytical placement algorithm,” in the 22nd VLSI Design/CAD Symposium, Yun-Lin, Taiwan, Aug. 2011
  30. H.-Y. Chang, H.-R. I. Jiang, and Y.-W. Chang, “Cost-effective timing ECO optimization,” in the 22nd VLSI Design/CAD Symposium, Yun-Lin, Taiwan, Aug. 2011
  31. M.-K. Hsu, Y.-W. Chang, and V. Balabanov, “TSV-aware analytical placement for 3D IC designs,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2011), San Diego, CA, Jun. 2011
  32. H.-Y. Chang, H.-R. I. Jiang, and Y.-W. Chang, “Simultaneous functional and timing ECO,” in Proceedings of ACM/IEEE Design Automation Conference (DAC-2011), San Diego, CA, Jun. 2011
  33. Y.-L. Chuang, S. Kim, Y. Shin, and Y.-W. Chang, “Pulsed-latch-aware placement for timing-integrity optimization,” ACM/IEEE Design Automation Conference (DAC-2010), Anaheim, CA, Jun. 2010
  34. C.-Y. Lin and Y.-W. Chang, “Cross contamination aware design methodology for pin-constrained digital microfludic biochips,” ACM/IEEE Design Automation Conference (DAC-2010), Anaheim, CA, Jun. 2010
  35. X.-W. Shih and Y.-W. Chang, “Fast timing-model independent clock-tree synthesis,” ACM/IEEE Design Automation Conference (DAC-2010), Anaheim, CA, Jun. 2010
  36. H.-Y. Chen, S.-J. Chou, and Y.-W. Chang, “Density gradient minimization with coupling-constrained dummy fill for CMP control,” Proceedings of ACM International Symposium on Physical Design (ISPD-2010), San Diego, CA, Mar. 2010
  37. X.-W. Shih, C.-C. Cheng, Y.-K. Ho, and Y.-W. Chang, “Blockage-avoiding buffered clock-tree synthesis for clock latency-range and skew minimization,” Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2010), Taipei, Taiwan, Jan. 2010
  38. K.-H. Ho, J.-H. Jiang, Y.-W. Chang, “TRECO: Dynamic technology remapping for timing engineering change orders,” Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2010), Taipei, Taiwan, Jan. 2010
  39. P. Falkenstern, Y. Xie, Y. Wang, and Y.-W. Chang, “Three-dimensional integrated circuit (3D IC) floorplan and power/ground network co-synthesis,” Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASP-DAC-2010), Taipei, Taiwan, Jan. 2010
  40. Y.-L. Chuang, P.-W. Lee, and Y.-W. Chang, “Voltage-drop aware analytical placement by global power spreading for mixed-size circuit designs,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2009), San Jose, Nov. 2009
  41. P.-W. Lee, C.-W. Lin, Y.-W. Chang, “An efficient pre-assignment routing algorithm for flip-chip designs,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2009), San Jose, Nov. 2009
  42. C.-H. Hsu, Y.-W. Chang, S. R. Nassif, “Simultaneous layout migration and decomposition for double patterning technology,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2009), San Jose, Nov. 2009
  43. T.-F. Chien, W.-C. Chao, Chien-Mo Li, K.-Y. Liao, Y.-W. Chang, M.-T. Chang, M.-H. Tsai, and C.-M. Tseng, “BIST design optimization for large-scale embedded memory cores,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2009), San Jose, Nov. 2009
  44. P.-W. Lee, C.-W. Lin, and Y.-W. Chang, “Fast pre-assignment flip-chip routing,” The 20th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2009
  45. X.-W. Shih, C.-C. Cheng, Y.-K. Ho, and Y.-W. Chang, “NTUclock: A high-quality blockage-avoiding buffered clock-tree router for modern circuit designs,” The 20th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2009
  46. T.-F. Chien, W.-C. Chao, Chien-Mo Li, K.-Y. Liao, Y.-W. Chang, M.-T. Chang, M.-H. Tsai, and C.-M. Tseng, “SoC memory BIST design optimization,” The 20th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2009
  47. K.-H. Ho, J.-H. Jiang, and Y.-W. Chang, “Technology remapping for ECO timing optimization,” The 20th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2009
  48. J.-W. Fang, D. F. Wong, and Y.-W. Chang, “Flip-chip routing with unified area-I/O pad assignments for package-board co-design,” Proceedings of ACM/IEEE Design Automation Conference (DAC-2009), San Francisco, CA, Jul. 2009
  49. C.-Y. Lin and Y.-W. Chang, “ILP-based pin-count aware design methodology for microfluidic biochips,” Proceedings of ACM/IEEE Design Automation Conference (DAC-2009), San Francisco, CA, Jul. 2009
  50. P.-H. Lin, H. Zhang, D. F. Wong, and Y.-W. Chang, “Thermal-driven analog placement considering device matching,” Proceedings of ACM/IEEE Design Automation Conference (DAC-2009), San Francisco, CA, Jul. 2009
  51. Z.-W. Jiang, M-K. Hsu, Y.-W. Chang, and K.-Y. Chao, “Spare-cell-aware multilevel analytical placement,” Proceedings of ACM/IEEE Design Automation Conference (DAC-2009), San Francisco, CA, Jul. 2009
  52. W.-P. Lee, D. Marculescu, and Y.-W. Chang, “Post-Floorplanning Power/Ground Ring Synthesis for Multiple-Supply-Voltage Designs,” Proceedings of ACM International Symposium on Physical Design (ISPD-2009), San Diego, CA, Apr. 2009
  53. H. Graeb, F. Balasa, R. Castro-Lopez, Y.-W. Chang, F. Fernandez, P.-H. Lin, M. Strasser, “Analog Layout Synthesis - Recent Approaches,” Proceedings of ACM/IEEE Design Automation and Test in Europe (DATE-2009), Niece, France, Mar. 2009
  54. C.-H. Hsu, H.-Y. Chen, and Y.-W. Chang, “High-performance global routing with fast overflow reduction,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2009), Yokohama, Japan, Jan. 2009
  55. J.-W. Fang and Y.-W. Chang, “Area-I/O flip-chip routing for chip-package co-design,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2008), San Jose, Nov. 2008
  56. J.-W. Fang, K.-H. Ho, and Y.-W. Chang, “Placement and routing for chip-package-board co-design considering differential pairs,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2008), San Jose, Nov. 2008
  57. C.-H. Hsu, H.-Y. Chen, and Y.-W. Chang, “Multi-layer global routing considering via and wire capacities,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2008), San Jose, Nov. 2008
  58. H.-C. Chen, Y.-L. Chuang, Y.-W. Chang, and Y.-C. Chang, “Constraint graph-based macro placement for mixed-size circuit designs,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2008), San Jose, Nov. 2008
  59. C.-H. Hsu, H.-Y. Chen, and Y.-W. Chang, “Fast global routing with forbidden-region rerouting,” The 19th VLSI Design/CAD Symposium, Ping-Tong, Taiwan, Aug. 2008
  60. C.-H. Hsu, H.-Y. Chen, and Y.-W. Chang, “Global routing with via/wire capacity considerations,” The 19th VLSI Design/CAD Symposium, Ping-Tong, Taiwan, Aug. 2008
  61. H.-Y. Chen, S.-J. Chou, and Y.-W. Chang, “Coupling-constrained dummy fill for density gradient minimization,” The 19th VLSI Design/CAD Symposium, Ping-Tong, Taiwan, Aug. 2008
  62. T.-C. Chen, G.-W. Liao, and Y.-W. Chang, “Predictive formulae for OPC with applications to lithography-friendly routing,” Proceedings of ACM/IEEE Design Automation Conference (DAC-2008), Anaheim, CA, Jun. 2008
  63. Z.-W. Jiang, B.-Y. Su, and Y.-W. Chang, “Routability-driven analytical placement by net overlapping removal for large-scale mixed-size designs,” Proceedings of ACM/IEEE Design Automation Conference (DAC-2008), Anaheim, CA, Jun. 2008
  64. P.-H. Yuh, S. Sapatnekar, C.-L. Yang, and Y.-W. Chang, “A progressive-ILP based routing algorithm for cross-referencing biochips,” Proceedings of ACM/IEEE Design Automation Conference (DAC-2008), Anaheim, CA, Jun. 2008
  65. T.-C. Chen, M. Cho, D. Z. Pan and Y.-W. Chang, “Metal-Density Driven Placement for CMP Variation and Routability,” Proceedings of ACM International Symposium on Physical Design (ISPD-2008), Portland, Oregon, Apr. 2008
  66. W.-P. Lee, H.-Y. Liu, K.-H. Ho, and Y.-W. Chang, “Sensitivity-Based Multiple-Vt Cell Swapping for Leakage Power Reduction Under Timing Requirements,” Proceedings of The 4th IEEE-TSA VLSI Design Automation and Test Conference (VLSI-DAT-2008), Hsinchu, Taiwan, Apr. 2008
  67. W.-P. Lee, H.-Y. Liu, and Y.-W. Chang, “An ILP algorithm for post-floorplanning voltage-island generation,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007
  68. Y.-P. Chen, J.-W. Fang, and Y.-W. Chang, “ECO timing optimization using spare cells and technology remapping,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007
  69. I.-J. Lin and Y.-W. Chang, “An efficient algorithm for statistical circuit optimization using Lagrangian relaxation,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007
  70. C.-W. Lin. S.-L. Huang, K.-C. Hsu, M.-X. Lee, and Y.-W. Chang, “Efficient multi-layer obstacle-avoiding rectilinear Steiner tree construction,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007
  71. H.-Y. Chen, S.-J. Chou, S.-L. Wang, and Y.-W. Chang, “Novel wire density driven full-chip routing for CMP variation control,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007
  72. P.-H. Yu, C.-L. Yang, and Y.-W. Chang, “BioRoute: A network flow based routing algorithm for digital microfluidic biochips,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2007), San Jose, Nov. 2007
  73. C.-F. Li, P.-H. Yuh, C.-L. Yang, and Y.-W. Chang, “Post-placement leakage optimization for partially dynamically reconfigurable FPGAs,” Proceedings of IEEE/ACM International Symposium on Low Power Electronic Design (ISLPED-07), Aug. 2007
  74. T.-C. Chen, G.-W. Liao, and Y.-W. Chang, “Lithography-aware routing with predictive OPC formulae,” The 18th VLSI Design/CAD Symposium, Hua-Lien, Aug. 2007
  75. H.-C. Chen, Y.-L. Chuang, and Y.-W. Chang, “A high quality transitive-closure-graph-based macro placer,” The 18th VLSI Design/CAD Symposium, Hua-Lien, Taiwan, Aug. 2007
  76. P-H. Yuh, C.-L. Yang, and Y.-W. Chang, “Placement of digital microfluidic biochips using the T-tree formulation,” ACM/IEEE Design Automation Conference (DAC-2006), pp. 931--934, San Francisco, CA, Jul. 2007
  77. J.-W. Fang, C.-H. Hsu, and Y.-W. Chang, “An integer linear programming algorithm for flip-chip routing,” Proceedings of ACM/IEEE Design Automation Conference (DAC-2007), San Diego, CA, Jun. 2007
  78. T.-C. Chen, P.-H. Yuh, Y.-W. Chang, F.-J. Liu, and D. Liu, “MP-trees: a packing-based macro placement algorithm for mixed-size designs,” Proceedings of ACM/IEEE Design Automation Conference (DAC-2007), San Diego, CA, Jun. 2007
  79. H.-Y. Liu, W.-P. Lee, and Y.-W. Chang, “A provably good approximation algorithm for power optimization using multiple supply voltages,” Proceedings of ACM/IEEE Design Automation Conference (DAC-2007), San Diego, CA, Jun. 2007
  80. Z.-W. Jiang, H.-C. Chen, T.-C. Chen, and Y.-W. Chang, “Challenges and solutions in modern VLSI placement,” Proceedings of The 3rd IEEE-TSA VLSI Design Automation and Test Conference (VLSI-DAT-2007), pp. 111--115, Hsinchu, Taiwan, Apr. 2007
  81. I.-J. Lin, T.-Y. Lin, and Y.-W. Chang, “Statistical circuit optimization considering device and interconnect process variations,” Proceedings of ACM International Workshop on System Level Interconnect Prediction (SLIP-2007), Austin, TX, Mar. 2007
  82. T.-C. Chen, Y.-L. Chuang, and Y.-W. Chang, “X-architecture placement based on effective wire models,” Proceedings of ACM International Symposium on Physical Design (ISPD-2007), pp. 87--94, Austin, TX, Mar. 2007
  83. C.-W. Lin, S.-Y. Chen, C.-F. Li, Y.-W. Chang, and C.-L. Yang, “Efficient obstacle-avoiding rectilinear Steiner tree construction,” Proceedings of ACM International Symposium on Physical Design (ISPD-2007), pp. 127--134, Austin, TX, Mar. 2007
  84. C.-W. Lin, M.-C. Tsai, K.-Y. Lee, T.-C. Chen, T.-C. Wang, and Y.-W. Chang, “Recent research and emerging challenges in physical design for manufacturability/reliability,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2007), pp. 238--243, Yokohama, Japan, Jan. 2007
  85. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, “A high quality analytical placer considering preplaced blocks and density constraint,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2006), pp. 187--192, San Jose, CA, Nov. 2006
  86. W.-P. Lee, H.-Y. Liu, and Y.-W. Chang, “Voltage island aware floorplanning for power and timing optimization,” /ACM International Conference on Computer-Aided Design (ICCAD-2006), pp. 389--394, San Jose, CA, Nov. 2006
  87. H.-Y. Liu, C.-W. Lin, S.-J. Chou, W.-T. Tu, Y.-W. Chang, and S.-Y. Kuo, “Current path analysis for electrostatic discharge protection,” IEEE/ACM International Conference on Computer-Aided Design (ICCAD-2006), pp. 510--515, San Jose, CA, Nov. 2006
  88. Z.-W. Jiang and Y.-W. Chang, “An optimal simultaneous diode/jumper insertion algorithm for antenna fixing,” /ACM International Conference on Computer-Aided Design (ICCAD-2006), pp. 669--674, San Jose, CA, Nov. 2006
  89. H.-Y. Chen, M.-F. Chiang, Y.-W. Chang, L. Chen, and B. Han, “Novel full-chip gridless routing considering double-via insertion,” ACM/IEEE Design Automation Conference (DAC-2006), pp. 755--760, San Francisco, CA, Jul. 2006
  90. C.-Y. Lai, S.-K. Jeng, Y.-W. Chang, and C.-C. Tsai,, “Surface integral inductance extraction for general interconnect structures,” International Symposium on Circuits and Systems (ISCAS-2006), Kos, Greece, May 2006
  91. C.-W. Liu and Y.-W. Chang, “Floorplan and power/ground network co-synthesis for fast design convergence,” ACM International Symposium on Physical Design (ISPD-2006), San Jose, CA, Apr. 2006
  92. B.-Y. Su, Y.-W. Chang, and J. Hu, “An optimal jumper insertion algorithm for antenna effect avoidance/fixing on general routing trees with obstacles,” ACM International Symposium on Physical Design (ISPD-2006), San Jose, CA, Apr. 2006
  93. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, “NTUplace2: a hybrid placer using partitioning and analytical techniques,” ACM International Symposium on Physical Design (ISPD-2006),, San Jose, CA, Apr. 2006
  94. Y.-W. Lin and Y.-W. Chang, “Thermal-driven interconnect optimization by gate and wire sizing,” The IEEE-TSA VLSI Design Automation and Test Conference (VLSI-DAT-2006), pp. 151--154, Hsinchu, Taiwan, Apr. 2006
  95. C.-Y. Peng, W.-C. Chao, Y.-W. Chang, and J.-H. Wang, “Simultaneous block and I/O buffer floorplanning for flip-chip design,” ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2006), pp. 213--218, Yokohama, Japan, Jan. 2006
  96. K. S.-M. Li, Y.-W. Chang, C.-C. Su, C.-L. Lee, and J. E. Chen, “P1500 based interconnect diagnosis for delay and crosstalk faults,” ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2006), pp. 366--371, Yokohama, Japan, Jan. 2006
  97. T.-C. Chen, Y.-W. Chang, and S.-C. Lin, “A novel framework for multilevel full-chip gridless routing,” ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2006), pp. 636--641, Yokohama, Japan, Jan. 2006
  98. B.-Y. Su and Y.-W. Chang, “An exact jumper insertion algorithm for antenna effect avoidance/fixing,” Proc. of ACM/IEEE Design Automation Conference (DAC-2005), Anaheim, CA, Jun. 2005
  99. T.-Y. Ho, C.-F. Chang, Y.-W. Chang, and S.-J. Chen, “Multilevel full-chip routing for the X-based architecture,” Proc. of ACM/IEEE Design Automation Conference (DAC-2005), Anaheim, CA, Jun. 2005
  100. S.-W. Tu, J.-Y. Jou, and Y.-W. Chang, “RLC coupling-aware simulation for on-chip buses and their encoding for delay reduction,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS-2005), Kobe, Japan, May 2005
  101. T.-C. Chen and Y.-W. Chang, “Modern floorplanning based on fast simulated annealing,” Proceedings of ACM International Symposium on Physical Design (ISPD-2005), San Francisco, CA, Apr. 2005
  102. T.-C. Chen, T.-C. Hsu, Z.-W. Jiang, and Y.-W. Chang, “NTUplace: a ratio partitioning based placement algorithm for large-scale mixed-size designs,” Proceedings of ACM International Symposium on Physical Design (ISPD-2005), San Francisco, CA, Apr. 2005
  103. S.-M Lee, C.-W. Lee, Y.-W. Chang, C.-C. Su, and J.-Y. Chen, “Multilevel full-chip routing with testability and yield enhancement,” Proceedings of ACM Interational Workshop on System Level Interconnect Prediction (SLIP-2005), San Francisco, CA, Apr. 2005
  104. S.-L. Wang and Y.-W. Chang, “Delay modelling for buffered RLC/RLY trees,” Proceedings of The 1st IEEE-TSA VLSI Design Automation and Test Conference (VLSI-DAT-2005), Hsinchu, Taiwan, Apr. 2005
  105. T.-C. Chen and Y.-W. Chang, “Multilevel gridless routing considering optical proximity effects,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2005), Shanghai, China, Jan. 2005
  106. J.-Y. Wuu, T.-C. Chen, and Y.-W. Chang, “SoC test scheduling using the B*-tree based flooprlanning technique,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2005), Shanghai, China, Jan. 2005
  107. G.-M. Wu, J.-M. Lin, Y.-W. Chang, and R.-H. Chuang, “Placement with symmetry constraints for analog layout design,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2005), Shanghai, China, Jan. 2005
  108. J.-M. Hsu and Y.-W. Chang, “A reusable methodology for non-slicing floorplanning,” Proceedings of IEEE Asia and Pacific Conference on Circuits and Systems (APCCAS-2004), Tainan, Taiwan, Dec. 2004
  109. P.-H. Yu, C.-L.Yang and Y.-W. Chang, “Temporal floorplanning using the T-tree formulation,” Proceedings of IEEE/ACM International Conference on computer-Aided Design (ICCAD-2004), San Jose, CA, Nov. 2004
  110. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, “Multilevel routing with jumper insertion for antenna avoidance,” Proceedings of IEEE International SOC Conference (SOC-2004), Santa Clara, California, Sept. 2004
  111. M.-C. Wu and Y.-W. Chang, “Placement with Alignment and Performance Constraints Using the B*-tree representation,” Proceedings of IEEE International Conference on Computer Design (ICCD-2004), San Jose, CA, Sept. 2004
  112. S.-W. Wu and Y.-W. Chang, “Efficient power/ground network analysis for power integrity driven design methodology,” Proc. of ACM/IEEE Design Automation Conference (DAC-2004), San Diego, CA, Jun. 2004
  113. S.-W. Tu, J.-Y. Jou, and Y.-W. Chang, “RLC effects on worst-case switching patterns for on-chip buses,” Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS-2004), Vancouver, Canada, May 2004
  114. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, “Multilevel routing with antenna avoidance,” Proceedings of ACM International Symposium on Physical Design (ISPD-2004), Phoenix, Arizona, Apr. 2004
  115. Y.-H. Cheng and Y.-W. Chang, “Integrating buffer planning with floorplanning for simultaneous multi-objective Optimization,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2004), pp. 624--627, Yokohama, Japan, Jan. 2004
  116. S.-W. Tu, J.-Y. Jou, and Y.-W. Chang, “Layout techniques for for on-chip interconnect inductance reduction,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2004), pp. 269-273, Yokohama, Japan, Jan. 2004
  117. P.-H. Yu, C.-L.Yang, Y.-W. Chang, and H.-L. Chen, “Temporal floorplanning using 3D-subTCG,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2004), pp. 725--730, Yokohama, Japan, Jan. 2004
  118. T. -Y. Ho, Y.-W. Chang, S.-J. Chen, and D. T. Lee,, “A fast crosstalk- and performance-driven multilevel routing system,”,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD),, pp. 382--387,, San Jose, Nov. 2003
  119. H.-C. Lee, Y.-W. Chang, J.-M. Hsu, and H. Yang,, “Multilevel floorplanning/placement for large-scale modules using B*-trees,” Proceedings of ACM/IEEE Design Automation Conference (DAC),, pp. 812--817,, Anaheim, CA, Jun. 2003
  120. H.-R. Jiang, Y.-W. Chang, J.-Y. Jou, and K.-Y. Chao,, “Simultaneous Floorplanning and Buffer Block Planning,”,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2003), pp. 431-434,, Kitakyushu, Japan,, Jan. 2003
  121. S.-M. Li, Y.-H. Cherng, and Y.-W. Chang, “, “Noise-aware buffer planning for interconnect-driven floorplanning,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2003), pp. 423-426,, Kitakyushu, Japan, Jan. 2003
  122. J.-M. Lin, S.-R. Pan, and Y.-W. Chang,, “Graph Matching-Based Algorithms for Array-Based FPGA Segmentation Design and Routing,” Proceedings of ACM/IEEE Asia South Pacific Design Automation Conference (ASP-DAC-2003), pp. 851-854, Kitakyushu, Japan, Jan. 2003
  123. S.-P. Lin and Y.-W. Chang,, “A novel framework for multilevel routing considering routability and performance,”,” Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD),, pp. 44-50, San Jose,, Nov. 2002
  124. J.-M. Lin and Y.-W. Chang, “, “TCG-S: Orthogonal Coupling of P*-admissible Representations for General Floorplans,” Proceedings of ACM/IEEE Design Automation Conference (DAC),, New Orleans,, Jun. 2002
  125. S.-W. Tu, W.-Z. Shen, Y.-W. Chang, and T.-C. Chen,, “On-chip inductance modeling for coplanar interconnects,” Proceedings of the IEEE Symposium on Circuits and Systems (ISCAS-2002), Pheonix, AZ, May 2002
  126. C.-Y. Chang, H.-R. Jiang, and Y.-W. Chang,, “Formulae for Performance Optimization and Their Applications to Interconnect-Driven Floorplanning,” Proceedings of the 2002 IEEE International Symposium on Quality of Electronic Design (ISQED),, San Jose, CA,, Mar. 2002
  127. J.-M. Lin, H.-L. Lin, and Y.-W. Chang,, “Arbitrary Convex and Concave Rectilinear Module Packing Using TCG,” Proceedings of ACM/IEEE Design Automation and Test in Europe (DATE),, pp. 69-75, Paris, France,, Mar. 2002
  128. G.-M. Wu, J.-M. Lin, M. C.-T. Chao, and Y.-W. Chang,, “Generic ILP-based partitioning algorithms for dynamically reconfigurable FPGAs,”,” Generic ILP-based partitioning algorithms for dynamically reconfigurable FPGAs,”, pp. 335-340,, Austin, TX, Sept. 2001
  129. G.-M. Wu, J.-M. Lin, and Y.-W. Chang,, “Precedence-constrained placement for dynamically reconfigurable FPGAs,” Proceedings of the 2001 IEEE International Conference on Computer Design (ICCD),, pp. 501-504,, Austin, TX, Sept. 2001
  130. T.-C. Chen, S.-R. Pan, and Y.-W. Chang,, “Performance optimization by wire/buffer sizing under the transmission line model,” Proceedings of the 2001 IEEE International Conference on Computer Design (ICCD),, pp. 192-197,, Austin, TX,, Sept. 2001
  131. J.-M. Lin and Y.-W. Chang,, “TCG: A transitive closure graph-based representation for non-slicing floorplans,” Proceedings of the 38th ACM/IEEE Design Automation Conference (DAC), pp. 764-769,, Las Vegas, NV,, Jun. 2001
  132. S.-R. Pan and Y.-W. Chang,, “Crosstalk-constrained performance optimization by using wire sizing and perturbation,”,” Proceedings of IEEE International Conference on Computer Design (ICCD),, pp. 581-584,, Austin, TX,, Sept. 2000
  133. G.-M. Wu, Y.-C. Chang, and Y.-W. Chang,, “Rectilinear block placement using B*-trees,” Proceedings of IEEE International Conference on Computer Design (ICCD),, pp. 351-356, Austin, TX,, Sept. 2000
  134. Y.-C. Chang, Y.-W. Chang, G.-M. Wu, and S.-W. Wu,, “B*-trees: A new representation for non-slicing floorplans,” Proceedings of the 37th ACM/IEEE Design Automation Conference (DAC),, pp. 458-463,, LA, CA,, Jun. 2000
  135. Y.-W. Chang and Y.-T. Chang,, “An architecture-driven simultaneous placement and routing for FPGAs,” Proceedings of the 37th ACM/IEEE Design Automation Conference (DAC, pp. 567-572,, LA, CA, Jun. 2000
  136. H.-R. Jiang, S.-R., Pan, Y.-W. Chang, and J.-Y. Jou,, “Reliable crosstalk-driven interconnect optimization,” in Proceedings of ACM International Symposium on Physical Design (ISPD),, pp. 128-133, San Diego, CA,, Apr. 2000
  137. C.-T. M. Chao, G.-M. Wu, H.-R. Jiang, and Y.-W. Chang,, “A clustering- and probability-based algorithm for time-multiplexed FPGA partitioning,” in Proceedings of IEEE/ACM International Conference on Computer-Aided Design (ICCAD), , pp. 364-368, San Jose, CA, Nov. 1999
  138. M. Shyu, Y.-D. Chang, G.-M. Wu, and Y.-W. Chang,, “Generic universal switch-block architecture and its interaction with routing,” Proceedings of IEEE International Conference on Computer Design (ICCD),, pp. 311-314,, Austin, TX,, Oct. 1999
  139. H.-R. Jiang, J.-Y. Jou, and Y.-W. Chang,, “Noise-constrained performance optimization by simultaneous wire and gate sizing based on Lagrangian relaxation,”,” Proceedings of the 36th ACM/IEEE Design Automation Conference (DAC9), pp. 90-95,, New Orleans, LA, Jun. 1999
  140. G.-M. Wu, M. Shyu, and Y.-W. Chang, “Three-dimensional universal switch modules,” Field Programmable Gate Arrays (FPGA), Monterey, CA,, Feb. 1999

Books:

  1. Y.-W. Chang, “Please see http://cc.ee.ntu.edu.tw/~ywchang/publications.html,” for his book publication list, 2016
  2. L.-T. Wang, Y.-W. Chang, and K.-T. Cheng (editors), “Electronic Design Automation: Synthesis, Verification, and Testing,” Elsevier/Morgan Kaufmann, USA, 934 pages, 2009, ISBN:978-0-12-374364-0
  3. T.-C. Chen and Y.-W. Chang, “Floorplanning (book chapter in Electronic Design Automation: Synthesis, Verification, and Testing),” Elsevier/Morgan Kaufmann, USA, 59 pages, 2009, ISBN:978-0-12-374364-0
  4. F. Y. Young, C.-K. Koh, and Y.-W. Chang, “Buffer planning (book chapter),” Physical Design Handbook (C. Alpert, S. Sapatnekar, and Dinesh D. Mehta, Editors), CRC Press, USA, 2008
  5. T.-C. Chen and Y.-W. Chang, “Packing floorplan representation (book chapter),” Physical Design Handbook (C. Alpert, S. Sapatnekar, and Dinesh D. Mehta, Editors), CRC Press, USA, 2008
  6. T.-C. Chen, Z.-W. Jiang, T.-C. Hsu, H.-C. Chen, and Y.-W. Chang, “NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs (book chapter),” G.-J. Nam and J. Cong, Editors, USA, 21 pages, 2007, ISBN:978-0-387-36837-5
  7. T.-Y. Ho, Y.-W. Chang, and S.-J. Chen, “ Full-chip Nanometer Routing Techniques,” Springer, USA, 102 pages, 2007, ISBN:978-1-4020-6194-3
  8. Y.-W. Chang, D. F. Wong, and C. K. Wong, “Programmable logic arrays,” ncyclopedia of Electrical and Electronics Engineering (John G. Webster, Editor), John Wiley & Sons, USA, Vol. 17, p pages, 1999, ISBN:0471-13958-0

Patents:

  1. Y.-W. Chang, “Please see http://cc.ee.ntu.edu.tw/~ywchang/publications.html,” for his patent list, 2016
  2. T.-C. Chen, Y.-W. Chang, and C.-C. Lin, “V-Shaped Multilevel Full-Chip Gridless Routing,” US 2007/0256045, 2010
  3. T.-C. Chen, P.-H. Yu, Y.-W. Chang, F.-J. Lin, and D. Liu, “Method of packing-based macro placement and semiconductor chip using the same,” US 2007/0157146, Dec. 2009
  4. T.-C. Chen, Y.-W. Chang, and C.-C. Lin,, “Multilevel IC Floorplanner,” US Patent 7,603,640, Oct. 2009

other:

  1. 陳泰蓁, 張耀文, “IC實體設計自動化所面臨的挑戰,” Jun. 2003, 零組件雜誌, pp. 68-74
  2. 張耀文, “在晶片平面規劃階段的電源/接地網合成,” Feb. 2003, 新電子月刊, 12頁
  3. 張耀文, 江蕙如, 周景楊, “拉式鬆綁法在電路最佳化之應用,” Sept. 2001, 工程科技通訊, 國科會, pp. 130-133