F. Y. Xie, B. C. Wu, and T.-T. Liu, “A Ripple Reduction Method for Switched-Capacitor DC-DC Voltage Converter Using Fully Digital Resistance Modulation,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 9, pp. 3631-3641, Sept. 2019
S. Y. Chang, B. C. Wu, Y. L. Liou, R. X. Zheng, P. L. Lee, T. D. Chiueh, and T.-T. Liu, “An Ultra-Low-Power Dual-Mode Automatic Sleep Staging Processor Using Neural-Network-Based Decision Tree,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 9, pp. 3504-3516, Sept. 2019
T.-S. Chen, D.-Y. Lee, T.-T. Liu, and A.-Y. Wu, “Dynamic Reconfigurable Ternary Content Addressable Memory for OpenFlow-Compliant Low-Power Packet Processing,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol.63, no.10, pp.1661-1672, Oct. 2016
T.-T. Liu and J. Rabaey, “A 0.25V 460nW Asynchronous Neural Signal Processor with Inherent Leakage Suppression,” IEEE Journal of Solid-State Circuits, vol.48, no.4, pp.897-906, Apr. 2013
D. Marković, C. C. Wang, L. Alarcón, T.-T. Liu , and J. Rabaey, “Ultra-Low Power Design in Near-Threshold Regime,” Proceedings of the IEEE, vol.98, no.2, pp.237–252, Feb. 2010
T.-T. Liu, L. Alarcón, M. Pierson, and J. Rabaey, “Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol.17, no.7, pp.883-892, Jul. 2009
L. Alarcon, T.-T. Liu, M. Pierson, and J. Rabaey, “Exploring Very Low-energy Logic: A Case Study,” Journal of Low Power Electronics, vol.3, no.3, pp.223-233, Dec. 2007
Conference & proceeding papers:
C.-M. Huang, T.-T. Liu, and T-D. Chiueh, “An Energy-Efficient Resilient Flip-Flop Circuit with Built-In Timing-Error Detection and Correction,” IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT’15), pp.1-4, Apr. 2015
J. Ryckaert, P. Raghavan, R. Baert, M.G. Bardon, M. Dusa, A. Mallik, S. Sakhare, B. Vandewalle, P. Wambacq, B. Chava, K. Croes, M. Dehan, D. Jang, P. Leray, T.-T. Liu, K. Miyaguchi, B. Parvais, P. Schuddinck, P. Weemaes, A. Mercha, J. Bommels, N. Horiguch, “Design Technology Co-optimization for N10,” IEEE Proceedings of the Custom Integrated Circuits Conference (CICC’14), pp.1-8, Sept. 2014
A. Mallik, P. Zuber, T.-T. Liu, B. Chava, B. Ballal, P. Royer, K. Croes, B. Rogier, R. Julien, A. Mercha, M. Badaroglu, and D. Verkest, “TEASE: A Systematic Analysis Framework for Early Evaluation of FinFET-based Advanced Technology Nodes,” 50th ACM/EDAC/IEEE Design Automation Conference (DAC’13), pp. 1-6, Jun. 2013
J. Richmond, M. John, L. Alarcón, W. Zhou, W. Li, T.-T. Liu, M. Alioto, S. Sanders, and J. Rabaey, “Active RFID: Perpetual Wireless Communications Platform for Sensors,” Proceeding of the 38th European Solid-State Circuits Conference, 2012. (ESSCIRC’12), pp. 434-437, Sept. 2012
T.-T. Liu and J. Rabaey, “A 0.25V 460nW Asynchronous Neural Signal Processor with Inherent Leakage Suppression,” IEEE Symposium on VLSI Circuits (VLSIC’12), pp. 158-159, Jun. 2012
T.-T. Liu and J. Rabaey, “Statistical Analysis and Optimization of Asynchronous Circuits,” 18th IEEE International Symposium on Asynchronous Circuits and Systems, (ASYNC'12), pp. 1-8, May 2012
L. Alarcón, T.-T. Liu, and J. Rabaey, “A Low-Leakage Parallel CRC Generator for Ultra-Low Power Applications,” Proceedings of 2011 IEEE International Symposium on Circuits and Systems (ISCAS’11), pp.2063-2066, May 2011
T.-T. Liu, L. Alarcón, M. Pierson, and J. Rabaey, “Asynchronous Computing in Sense Amplifier-based Pass Transistor Logic,” 14th IEEE International Symposium on Asynchronous Circuits and Systems, (ASYNC '08), pp.105-115, Apr. 2008