簡韶逸教授的個人資料 - Profile of Shao-Yi Chien

簡韶逸 Shao-Yi Chien

國立台灣大學電機工程學系 教授
Professor, Department of Electrical Engineering, National Taiwan University

主要研究領域:

多媒體訊號處理系統、多媒體積體電路設計、晶片系統設計方法研究

Major Research Areas:

Multimedia signal processing systems, multimedia VLSI design, and System-on-a-Chip design methodology

研究領域摘要:

簡教授主持媒體晶片系統實驗室。研究領域包括多媒體訊號處理系統、多媒體積體電路設計、以及晶片系統設計方法研究，從演算法層次涵括到硬體晶片設計層次到系統設計層次。近年之研究重點為智慧型視訊處理系統、影像信號處理系統、繪圖晶片設計、以及影像及視訊編碼系統。

Research Summary:

Prof. Chien directs Media IC & System Design Lab. The research area includes multimedia signal processing systems, multimedia VLSI design, and System-on-a-Chip design methodology. The research level is from algorithm level, hardware architecture level, to system level. The current research directions of Media IC & System Design Lab are intelligent video signal processing systems, image signal processing systems, graphics processing unit design, and image/video coding systems.

Photo of Shao-Yi Chien

代表性著作 Selected Publication

  1. Guan-Lin Wu, Tung-Hsing Wu, and Shao-Yi Chien, “Algorithm and architecture design of perception engine for video coding applications,” IEEE Transactions on Multimedia, vol. 13, no. 6, pp. 1181—1194, Dec. 2011
  2. Chia-Ming Chang, Yu-Jung Chen, Yen-Chang Lu, Chun-Yi Lin, Liang-Gee Chen, and Shao-Yi Chien, “A 172.6mW 43.8GFLOPS energy-efficient scalable eight-core 3D graphics processor for mobile multimedia applications,” IEEE Asian Solid-State Circuits Conference 2011 (A-SSCC), Jeju, Korea, Nov. 2011
  3. Jui-Hsin Lai, Chieh-Li Chen, Po-Chen Wu, Chieh-Chi Kao, and Shao-Yi Chien, “Tennis Real Play: an interactive tennis game with models from real videos,” ACM Multimedia (MM 2011), pp.1213-1216, Scottsdale, Arizona, USA, Nov. 2011
  4. Guan-Lin Wu, Ching-Yi Chen, and Shao-Yi Chien, “Algorithm and Architecture Design of Image Inpainting Engine for Video Error Concealment Applications,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 21, no. 6, pp. 792—803, Jun. 2011
  5. Tse-Wei Chen, Chi-Sun Tang, Sung-Fang Tsai, Chen-Han Tsai, Shao-Yi Chien, and Liang-Gee Chen, “Tera-Scale Performance Machine Learning SoC (MLSoC) With Dual Stream Processor Architecture for Multimedia Content Analysis,” IEEE Journal of Solid-State Circuits, vol. 45, no. 11, pp. 2321--2329, Nov. 2010
  6. Guan-Lin Wu, Ching-Yi Chen, Tung-Hsing Wu, and Shao-Yi Chien, “Efficient Spatial-Temporal Error Concealment Algorithm and Hardware Architecture Design for H.264/AVC,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 20, no. 11, pp. 1409-1422, Nov. 2010
  7. Tse-Wei Chen and Shao-Yi Chien, “Bandwidth adaptive hardware architecture of K-Means clustering for video analysis,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 18, no. 6, pp. 957 - 966, Jun. 2010
  8. Tse-Wei Chen, Yi-Ling Chen, Teng-Yuan Cheng, Chi-Sun Tang, Pei-Kuei Tsung, Tzu-Der Chuang, Liang-Gee Chen, Shao-Yi Chien, “A multimedia semantic analysis SoC (SASoC) with machine-learning engine,” Internal Solid-State Circuits Conference (ISSCC2010), pp. 338-339, San Francisco, USA, Feb. 2010
  9. Chih-Hao Sun, Ka-Hang Lok, You-Ming Tsao, Chia-Ming Chang, and Shao-Yi Chien, “CFU: multi-purpose configurable filtering unit for mobile multimedia applications on graphics hardware,” High Performance Graphics (HPG 2009), New Orleans, Louisiana, USA, Aug. 2009
  10. Chih-Hao Sun, You-Ming Tsao, and Shao-Yi Chien, “High-quality mipmapping texture compression with alpha maps for graphics processing units,” IEEE Transactions on Multimedia, vol. 11, no. 4, pp. 589-599, Jun. 2009
  11. Wei-Kai Chan, Jing-Ying Chang, Tse-Wei Chen, and Shao-Yi Chien, “Efficient content analysis engine for visual surveillance network,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 19, no. 5, pp. 693-703, May 2009
  12. Jason C. Chen and Shao-Yi Chien, “CRISP: coarse-grained reconfigurable image stream processor for digital still cameras and camcorders,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 18. no. 9, pp. 1223-1236, Sept. 2008
  13. Shao-Yi Chien, You-Ming Tsao, Chin-Hsiang Chang, and Yu-Cheng Lin, “An 8.6mW 25Mvertices/s 400-MFLOPS 800-MOPS 8.91mm2 multimedia stream processor core for mobile applications,” IEEE Journal of Solid-State Circuits, vol. 43, no. 9, pp. 2025-2035, Sept. 2008
  14. Jason C. Chen, Chun-Fu Shen, and Shao-Yi Chien, “Coarse-grained reconfigurable image stream processor for digital still cameras and camcorders,” Proc. of IEEE Custom Integrated Circuits Conference (CICC2007), San Jose, USA, Sept. 2007
  15. You-Ming Tsao, Chin-Hsiang Chang, Yu-Cheng Lin, Shao-Yi Chien, and Liang-Gee Chen, “An 8.6mW 12.5Mvertices/s 800MOPS 8.91mm2 stream processor core for mobile graphics and video applications,” Digest of Technical Papers of Symposium on VLSI Circuits, Kyoto, Japan, Jun. 2007
  16. Shao-Yi Chien, Bing-Yu Hsieh, Yu-Wen Huang, Shyh-Yih Ma, and Liang-Gee Chen, “Hybrid morphology processing unit architecture for moving object segmentation systems,” Journal of VLSI Signal Processing, vol. 42, no. 3, pp. 241-255, Mar. 2006
  17. Shao-Yi Chien, Yu-Wen Huang, Bing-Yu Hsieh, Shyh-Yih Ma, and Liang-Gee Chen, “Fast video segmentation algorithm with shadow cancellation, global motion compensation, and adaptive threshold techniques,” IEEE Transactions on Multimedia, vol. 6, no. 5, pp. 732-748, Oct. 2004
  18. Shao-Yi Chien, Shyh-Yih Ma, and Liang-Gee Chen, “Efficient moving object segmentation algorithm using background registration technique,” IEEE Transactions on Circuits and Systems for Video Technology, vol. 12, no. 7, pp. 577-586, Jul. 2002