Major Research Areas

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Research Summary

    Chung-Ping Chen (陳中平) Charlie Chung-Ping Chen received his B.S degree in computer science and information engineering from the National Chiao-Tung University,
Hsinchu, Taiwan, in 1990 and his M.S. and Ph.D. degrees in computer science from
the University of Texas at Austin in 1996 and 1998. From 1996-1999 he was with Intel Corporation as a senior CAD engineer with Strategic CAD Labs. Since 1999, he has been an assistant professor in the ECE Department at the University of Wisconsin, Madison. Since 2003, he has been an associate professor in the EE department of National Taiwan University, Taiwan. His research interests are in the areas of computer-aided design and microprocessor circuit design with an emphasis on interconnect and circuit optimization, circuit simulation, and signal/power/thermal integrity analysis and optimization.

Prof. Chen served the program committee for most of the major VLSI Design Automation Conferences which include DAC, ICCAD, DAC, DATE, ISPD, ISQED, ASPDAC, and SASIMI. Prof. Chen received the D2000 award from Intel Corp. and National Sciences Foundation Faculty Early Career Development Award (CAREER) at 1999 and 2001, respectively. He also received the 2002 Sigda/ACM Outstanding Young Faculty award and 2002 Peter Schneider Faculty Development award．He received the best paper award from the International Symposium Physical Design, 2003.

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Journal articles & book chapters

1. Rong Jiang, Wenyin Fu and Charlie Chung-Ping Chen, “EPEEC: A Compact Eddy-Current-Aware Reluctance-Based Macromodel for High-Speed Interconnects above Lossy Multilayer Substrate” , IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD) , Jan. 2005

2. Lizheng Zhang, Weijen Chen, Yuhen Hu and Charlie Chungping Chen, “Statistical Static Timing Analysis with Conditional Linear MAX/MIN Approximation and Extended Canonical Model” , IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD) , Jan. 2005

3. Jeng-Laing Tsai, Tsung-Hao Chen, and Charlie Chung-Ping Chen, “Zero-Skew Clock-Tree Optimization with Buffer-Insertion/Sizing and Wire-Sizing” , IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD) , Vol. Vol. 23 , No. 4, pp. 565-572-, Apr. 2004

4. Yu-Min Lee, Yahong Cao, Tsung-Hao Chen, Janet Wang and Charlie Chung-Ping Chen, “HiPRIME: Hierarchical and Passivity Preserved Interconnect Macromodeling Engine for RLKC Power Delivery” , IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD) , Jan. 2004

5. 1. Yu-Min Lee and Charlie Chung-Ping Chen,, “The Power Grid Transient Simulation in Linear Time based on 3D Alternating-Direction-Implicit Method” , IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD) , Vol. Vol. 22, No. 11 , pp1545-1550,-, Nov. 2003

6. 2. Ting-Yuan Wang and Charlie Chung-Ping Chen,, “Thermal-ADI: A Linear-Time Chip-Level Dynamic Thermal Simulation Algorithm Based on Alternating-Direction-Implicit (ADI) Method” , IEEE Transaction on Very Large Scale Integration Systems (TVLSI), , Vol. Vol. 11, No. 4, , pp691- 700-, Aug. 2003

7. 3. Tsung-Hao Chen, Clement Luk, and Charlie Chung-Ping Chen,, “INDUCTWISE: Inductance-Wise Interconnect Simulator and Extractor” , IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), , Vol. Vol. 22, No. 7, , pp884-894,-, Jul. 2003

8. 4. Ting-Yuan Wang and Charlie Chung-Ping Chen,, “3-D Thermal-ADI: a linear-time chip level transient thermal simulator” , IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD) , Vol. Vol. 21, No. 11, , pp1343 -1352,-, Nov. 2002

9. 6. Yu-Min Lee, Charlie Chung-Ping Chen, and D. F. Wong, “Optimal Wire-sizing Function under the Elmore Delay Model with Bounded Wiresizes” , IEEE Transactions on Circuits & Systems-I (TCAS-I) , Vol. Vol. 49, No. 11, , pp1671-1677,-, Nov. 2002

10. Yu-Min Lee and Charlie Chung-Ping Chen, “Power Grid Transient Simulation in Linear Time based on Transmission-Line-Modeling Alternating-Direction-Implicit Method” , IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD) , Vol. Vol. 21, No. 11 , pp1343 -1352-, Nov. 2002

11. 7. Chung-Ping Chen, Chris C. N. Chu, and D. F. Wong,, “Fast and Exact Simultaneous Gate and Wire Sizing by Lagrangian Relaxation” , IEEE Transactions on Computer-Aided Design of Integrated Circuits And Systems (TCAD) , Vol. Vol. 18, No. 7 , pp1014-1025,-, Jul. 1999

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Conference & proceeding papers:

1. Jeng-Liang Tsai, DongHyun Baik, Charlie Chung-Ping Chen and Kewal K. Saluja, “False Path and Clock Scheduling Based Yield-Aware Gate Sizing” , VLSI Design , Jan. 2005

2. Jeng-Liang Tsai and Charlie Chung-Ping Chen, “Process-Variation Robust and Low-Power Zero-Skew Buffered Clock-Tree Synthesis Using Projected Scan-Line Sampling” , ASPDAC , Jan. 2005

3. Lizheng Zhang, Yu-Hen Hu and Charlie Chung-Ping Chen, “Block-Based Statistical Timing Analysis with Extended Canonical Timing Model” , ASPDAC , Jan. 2005

4. Rong Jiang and Charlie Chung-Ping Chen, “Comprehensive Frequency Dependent Interconnect Extraction and Evaluction Methodology” , ASPDAC , Jan. 2005

5. Hsinwei Chou, Yu-Hao Wang and Charlie Chung-Ping Chen, “Fast and Effective Gate-Sizing with Multiple-Vt Assignment using Generalized Lagrangian Relaxation” , ASPDAC , Jan. 2005

6. Lizheng Zhang, Weijen Chen, Yu-Hen Hu and Charlie Chung-Ping Chen, “Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model” , DATE , Jan. 2005

7. Qi-Wei Kuo, Vikas Sharma and Charlie Chung-Ping Chen, “Substrate-Bias Optimized 0.18um 2.5 GHz 32-bit adder with Post-Manufacture Tunable Clock” , VLSI-TSA-DAT , Jan. 2005

8. Vikas Sharma, Chien-Liang Chen and Charlie Chung-Ping Chen, “1-V 7-mW Dual-Band Fast-Locked Frequency Synthesizer” , GLSVLSI , Jan. 2005

9. Rong Jiang and Charlie Chung-Ping Chen, “ICCAP: A Linear Time Sparse Transformation and Reordering Algorithm for 3D BEM Capacitance Extraction” , DAC , Jan. 2005

10. Lizheng Zhang, Weijen Chen, Yuhen Hu, John A. Gubner and Charlie Chung-Ping Chen, “Correlation-Preserved Non-Gaussian Statistical Timing Analysis with Quadratic Timing Model” , DAC , Jan. 2005

11. Jeng-Liang Tsai, Lizheng Zhang and Charlie Chung-Ping Chen, “Statistical Timing Analysis Driven Post-Silicon-Tunable Clock-Tree Synthesis” , ICCAD , Jan. 2005

12. Sanghamitra Roy, Weijen Chen and Charlie Chung-Ping Chen, “ConvexFit: An Optimal Minimum-Error Convex Fitting and Smoothing Algorithm with Application to Gate-Sizing” , ICCAD , Jan. 2005

13. Rong Jiang, Wenyin Fu, Janet Meiling Wang and Charlie Chung-Ping Chen, “Efficient Statistical Capacitance Variability Modeling with Orthogonal Principle Factor Analysis” , ICCAD , Jan. 2005

14. Rong Jiang, Yu-hao Wang, and Charlie Chung-Ping Chen, “Linear Time Capacitance Extraction based on Implicit Congruence Transformation” , International Microwave Symposium (IMS) , Jan. 2005

15. Lizheng Zhang, Yu-Hen Hu and Charlie Chung-Ping Chen, “Wave-Pipelined On-Chip Global Interconnect” , ASPDAC , Jan. 2005

16. Lizheng Zhang, Yuhen Hu, and Charlie Chung-Ping Chen, “Wave-pipelined On-Chip Global Interconnect” , ACM/IEEE TAU Workshop on Timing Issues in the Specification and Synthesis of Digital Systems , Jan. 2004

17. Rong Jiang and Charlie Chung-Ping Chen, “Realizable Reduction for Electromagnetically Coupled RLMC Interconnects” , Design, Automation and Test in Europe Conference and Exhibition (DATE) , Jan. 2004

18. Rong Jiang and Charlie Chung-Ping Chen, “SCORE: SPICE Compatible Reluctance Extraction” , Design, Automation and Test in Europe Conference and Exhibition (DATE) , Jan. 2004

19. [26] Ting-Yuan Wang, Jeng-Liang Tsai, and Charlie Chung-Ping Chen, “Thermal and Power Integrity based Power/Ground Networks Optimization” , Design, Automation and Test in Europe Conference and Exhibition (DATE) , Jan. 2004

20. Ting-Yuan Wang and Charlie Chung-Ping Chen, “SPICE-Compatible Thermal Simulation with Lumped Circuit Modeling for Thermal Reliability Analysis based on Model Reduction” , 5th International Symposium on Quality Electronic Design (ISQED) , Jan. 2004

21. Ting-Yuan Wang, Jeng-Liang Tsai, and Charlie Chung-Ping Chen, “Power-Delivery Networks Optimization with Thermal Reliability Integrity” , ACM International Symposium on Physical Design (ISPD) , Jan. 2004

22. Rong Jiang and Charlie Chung-Ping Chen, “ESPRIT: A Compact Reluctance Based Interconnect Model Considering Lossy Substrate Eddy Current” , International Microwave Symposium (IMS) , Jan. 2004

23. Lizheng Zhang, Yu Hen Hu, and Charlie Chung-Ping Chen, “Statistical Timing Analysis in Sequential Circuit for On-Chip Global Interconnect Pipelining” , IEEE/ACM Design Automation Conference (DAC) , Jan. 2004

24. Rong Jiang and Charlie Chung-Ping Chen, “EPEEC: A Compact Reluctance Based Interconnect Model Considering Lossy Substrate Eddy Currents” , IEEE Custom Integrated Circuits Conference (CICC) , Jan. 2004

25. Lizheng Zhang, Yu-Hen Hu and Charlie Chung-Ping Chen, “Statistical Timing Analysis with AMECT: Asymptotic MAX/MIN Approximation and Extended Canonical Timing Model” , The 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) , Jan. 2004

26. Hsinwei Chou and Charlie Chung-Ping Chen, “A ROBDD-Based Generalized Nodal Control Scheme for Standby Leakage Power Reduction” , The 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) , Jan. 2004

27. Hsinwei Chou, Yu-Hao Wang and Charlie Chung-Ping Chen, “LARTTE: A Posynomial-Based Lagrangian Relaxation Tuning Tool for Fast and Effective Gate-Sizing and Multiple Vt Assignment” , The 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI) , Jan. 2004

28. Jeng-Liang Tsai, DongHyun Baik, Charlie Chung-Ping Chen and Kewal K. Saluja, “A Yield Improvement Methodology Using Pre- and Post-Silicon Statistical Clock Scheduling” , IEEE/ACM International Conference on Computer-Aided Design (ICCAD) , Jan. 2004

29. Tsung-Hao Chen, Jeng-Liang Tsai, Charlie Chung-Ping Chen and Tanay Karnik, “HiSIM: Hierarchical Interconnect-Centric Circuit Simulator” , IEEE/ACM International Conference on Computer-Aided Design (ICCAD) , Jan. 2004

30. 2. Rong Jiang, Tsung-Hao Chen, and Charlie Chung-Ping Chen,, “PODEA: POwer Delivery Efficient Analysis with Realizable Model Reduction” , IEEE International Symposium on Circuits and Systems (ISCAS , May 2003

31. 3. Ting-Yuan Wang, Yu-Min Lee, and Charlie Chung-Ping Chen,, “3D Thermal-ADI: An Efficient Chip-Level Transient Thermal Simulator” , ACM International Symposium on Physical Design (ISPD) , Apr. 2003

32. 4. Jeng-Laing Tsai, Tsung-Hao Chen, and Charlie Chung-Ping Chen,, “Epsilon-Optimal Zero-Skew Clock Tree Wire-Sizing in Pseudo-Polynomial Time” , ACM International Symposium on Physical Design (ISPD), , Apr. 2003

33. Yu-Min Lee and Charlie Chung-Ping Chen,, “The Power Grid Transient Simulation in Linear Time based on 3D Alternating-Direction-Implicit Method” , Design, Automation and Test in Europe Conference and Exhibition (DATE) , Feb. 2003

34. 1. Tsung-Hao Chen, Clement Luk, and Charlie Chung-Ping Chen,, “SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation” , IEEE/ACM International Conference on Computer-Aided Design (ICCAD), , Jan. 2003

35. 6. Tsung-Hao Chen, Clement Luk, Hyungsuk Kim, and Charlie Chung-Ping Chen,, “INDUCTWISE: Inductance-Wise Interconnect Simulator and Extractor” , IEEE/ACM Design Automation Conference (DAC) , Jan. 2002

36. 7. Yahong Cao, Yu-Min Lee, Tsung-Hao Chen, and Charlie Chung-Ping Chen,, “HiPRIME: Hierarchical and Passivity Reserved Interconnect Macromodeling Engine for RLKC Power Delivery” , IEEE/ACM Design Automation Conference (DAC), , Jan. 2002

37. 8. Ting-Yuan Wang and Charlie Chung-Ping Chen,, “Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm” , 3rd International Symposium on Quality Electronic Design (ISQED) , Jan. 2002

38. 9. Yu-Min Lee and Charlie Chung-Ping Chen, ", “Power Grid Transient Simulation in Linear Time Based on Transmission-Line-Modeling Alternating-Direction-Implicit Method” , IEEE/ACM International Conference on Computer Aided Design (ICCAD) , Jan. 2001

39. 10. Saisanthosh Balakrishnan, Jong Hyuk Park, Hyungsuk Kim, Yu-Min Lee and Charlie Chung-Ping Chen,, “Linear Time Hierarchical Capacitance Extraction Without Multipole Expansion” , " International Conference on Computer Design (ICCD) , Jan. 2001

40. 11. Pradeepsunder Ganesh and Charlie Chung-Ping Chen, “RC-in RC-out Model Order Reduction Accurate Up to Second Order Moments” , International Conference on Computer Design (ICCD) , Jan. 2001

41. 12. Tsung-Hao Chen and Charlie Chung-Ping Chen,, “Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods” , IEEE/ACM Design Automation Conference (DAC), , Jan. 2001

42. Ting-Yuan Wang and Charlie Chung-Ping Chen, “Thermal-ADI: A Linear-Time Chip-Level Dynamic Thermal Simulation Algorithm Based on Alternating-Direction-Implicit (ADI) Method” , ACM International Symposium on Physical Design (ISPD) , Jan. 2001

43. 14. Yu-Min Lee, Hing Yin Lai, and Charlie Chung-Ping Chen,, “Optimal spacing and capacitance padding for general clock structures” , Asian and South Pacific Design Automation Conference (ASP-DAC), , Jan. 2001

44. 15. Yu-min Lee and Charlie Chung-Ping Chen,, “Hierarchical model order reduction for signal-integrity driven interconnect synthesis” , Great Lakes Symposium on VLSI (GLSVLSI) , Jan. 2001

45. 16. Charlie Chung-Ping Chen, Narayanan Murugesan, Tae-Woo Lee, and Susan C. Hagness, “FDTD-ADI: An Unconditionally Stable Full Wave Maxwell Equation Solver for VLSI Modeling” , " IEEE/ACM International Conference on Computer Aided Design (ICCAD), , Jan. 2000

46. 17. Chung-Ping Chen and N. Menezes,, “Noise-Aware Repeater Insertion and Wire-Sizing for On-chip Interconnect Using Hierarchical Moment-Matching” , IEEE/ACM Design Automation Conference (DAC), , Jan. 1999

47. 18. Chung-Ping Chen and D.F. Wong, ", “Error-bounded Pade Approximation via Bilinear Conformal Transformation” , IEEE/ACM Design Automation Conference (DAC) , Jan. 1999

48. 19. N. Menezes and Chung-Ping Chen, “Spec-based Repeater Insertion and Wire-Sizing for On-chip Interconnect” , Twelfth International Conference on VLSI Design, , Jan. 1999

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