Major Research Areas

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Research Summary

    James B. Kuo (郭正邦) Professor James B. Kuo received a BSEE degree from National Taiwan University in 1977, an MSEE degree from Ohio State University in 1978, and a PhDEE degree from Stanford University in 1985. Before the PhDEE program, he worked in Penril Data Communications and Racal Vadic(1978-1981) as a research engineer working on integrating telecommunication modem chips using CMOS technology. After the PhD program (1985-1987), he worked as an engineering research associate in IC Lab of Stanford University, working on BiCMOS devices. In 1987 he joined National Taiwan University as an associate professor and since 1990 he has been a professor. Between 2000 and 2002 he has been a chair professor at the University of Waterloo, Canada, on leave from NTUEE. His research expertise is in the field of low-voltage CMOS VLSI circuits and SPICE compact modeling of deep-submicron bulk and SOI CMOS and BiCMOS VLSI devices. He served as an associate editor for the IEEE Circuits and Devices Magazine and the VP membership for the IEEE Electron Devices Society. He has been awarded an IEEE fellow award in 1999 for contributions to modeling CMOS VLSI devices. He has won the NSC Outstanding Research Award three times in 1996, 2000 and 2002. In 2007, he has been awarded the prestigious NTU Life Distinguished Professor.

    He is also an IEEE distinguished lecturer. He has published 300 technical papers. He holds 16 invention patents including 7 US patents on low-voltage CMOS VLSI circuits. As a highly recognized expert, he authored nine books including Low-Voltage SOI CMOS VLSI Devices and Circuits (John Wiley: New York 2001), Low-Voltage CMOS VLSI Circuits (John Wiley: New York, 1999) and CMOS VLSI Engineering: Silicon-On-Insulator (SOI)---Kluwer: Boston, 1998. As a technical leader, he has graduated 80 MS and PhD students specialized in CMOS circuit designs and device modeling, currently working in leading US and Taiwan's microelectronics companies.

    Dr. Kuo's Personal Homepage

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Journal articles & book chapters

1. C Hong, L. Yang, Q. Cheng, T. Han, J. B. Kuo, Y. Chen, “A Continuous Compact Model Incorporating Higher-Order Correction for Junctionless Nanowire Tansistors with Arbitrary Doping Profiles” , IEEE Trans. on Nanotechnology , Vol. Vol. 15, No. 4 , 657-665, Jul. 2016

2. C. Hong, Q Cheng, P. Wang, L. Yang, Y. B. Kuo, Y. Chen, “An Analytic Surface-Field-Based Quasi-Atomistic Model for Nanowire MOSFETs with Random Dopant Fluctuations” , IEEE Trans. Electron Devices , Vol. Vol. 62, No. 12 , 4179-4186, Dec. 2015

3. Q. Cheng, C. Y. Hong, J. B. Kuo, Y. J. Chen, “A Surface-Field-Based Model for Nanowire MOSFETs with Spatial Variations of Doping Profiles” , IEEE Transactions on Electron Devices , Vol. 61 , pp. 4040-4046-, Dec. 2014

4. L. L. Wang, J. B. Kuo, S. Zhang, “Analytical Drain Current Model for Poly-Si Thin-Film Transistors Biased in Strong Inversion Considering Degradation of Tail States at Grain Boundary” , IEEE Transactions on Electron Devices , Vol. 60 , Mar. 2013

5. T. C. Liu, J. B. Kuo and S. D. Zhang, “A Closed-form Analytical Transient Response Model for On-Chip Distortionless Interconnect” , IEEE Transactions on Electron Devices , Vol. 59 , pp.3186-3192-, Dec. 2012

6. T. C. Liu, J. B. Kuo and S. D. Zhang, “Foating-Body Kink-Effect Related Parasitic Bipolar Transistor Behavior in Poly-Si TFT” , IEEE Transactions on Electron Devices , Vol. 33 , pp.842-844-, Jun. 2012

7. C. H. Chen, J. B. Kuo, D. Chen, and C. S. Yeh, “Function of Parasitic Bipolar Transistor in the 40nm SOI NMOS Device Considering the Floating Body Effect” , Solid State Electronics , Vol. 70 , pp.3-7-, Apr. 2012

8. H. J. Hung, J. B. kuo, D. Chen, C. T. Tsai and C. S. Yeh, “Shallow trench isolation-related narrow channel effect on the kink effect behaviour of 40nm PD SOI NMOS device” , Solid-State Electronics , Vol. 54 , pp.609-611-, May 2010

9. H. J. Hung, J. B. Kuo, D. Chen and C. S. Yeh, “Gate Tunneling Leakage Curent Behaviour of 40nm PD SOI NMOS Device Consdering Floating Body Effect” , Microelectronics Reliability , pp. 607-609-, May 2010

10. C. H. Lin and J. B. Kuo, “Closed-Form Partitioned Gate Tunneling Current Model for NMOS Devices with an Ultra-thin Gate Oxide” , Solid State Electronics , Vol. Vol. 53, No. 11 , pp. 1191-1197-, Nov. 2009

11. I. S. Lin and J. B. Kuo, “Analysis of STI-Induced Mechanical Stres-Related Kink Effect of 40nm PD SOI NMOS Devices Biased in Saturation Region” , Solid-State Electronics , Vol. 52 , 12-, Dec. 2008

12. I. S. Lin, V. C. Su, J. B. Kuo, D. Chen, C. S. Yeh, C. T. Tsai, M. Ma, “Breakdown Behavior of 40-nm PD-SOI NMOS Device Considering STI-Induced Mechanical Stress Effect” , IEEE Electron Device Letters , Vol. Vol. 29 , pp. 612-614-, Jun. 2008

13. I. S. Lin, V. C. Su, J. B. Kuo, R. Lee, G. S. Lin, D. Chen, C. S. Yeh, C. T. Tsai and M. Ma, “Shallow-Trench-Isolation (STI)-Induced Mechanical-Stress-Related Kink-Effect Behaviors of 40-nm PD SOI NMOS Devices” , IEEE Transactions Electron Devices , Vol. Vol. 55 , 1558-1562-, Jun. 2008

14. B. Chung and J. B. Kuo, “Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique for SOC Application” , Integration, the VLSI Journal , Vol. Vol. 42 , pp. 9-16-, Jan. 2008

15. H. H. Lin and J. B. Kuo, “Narrow Band Gap Semiconductor” , Wiley's Electrical Engineering Encyclopedia , Dec. 2007

16. H. H. Lin and J. B. Kuo, “Narrow Bandgap Semiconductor” , Wiley Encyclopedia , Dec. 2007

17. C. C. Chen, J. B. Kuo, K. W. Su, and S. Liu, “Analysis of the Gate Source/Drain Capacitance Behavior of a Narrow-Channel FD SOI NMOS Device Considering the 3D Fringing Capacitances Using 3D Simulation” , IEEE Trans. Electron Devices , Vol. Vol. 53, No. 10 , pp. 2559-2563-, Oct. 2006

18. Y. S. Lin, C. H. Lin, J. B. Kuo, and K. W. Su, “Gate Capacitances Behavior of Nanometer FD SOI CMOS Devices with HfO2 High-k Gate Dielectric Effects Using 2D Simulation” , IEEE Transactions on Electron Devices , Vol. Vol. 53, No. 6 , pp. 1373-1378-, Jun. 2006

19. C. H. Lin, J. B. KUo, K. W. Su and S. Liu, “Partitioned Gate Tunneling Current Model Considering Distributed Effects for CMOS Devices with an Ultra-thin (1nm) Gate Oxide” , IEE Electronics Letters , Vol. Vol. 42, No. 3 , pp.182-184-, Feb. 2006

20. T. Y. Chiang and J. B. Kuo, “0.7V Manchester Carry Look-Ahead Circuit Using PD SOI CMOS Asymmetrical Dynamic Threshold Pass Transistor Techniques Suitable for Low-Voltage CMOS VLSI Systems” , IEE Proceddings on Circuits, Devices and Systems , Vol. Vol. 152, Issue 2 , pp. 123-126-, Apr. 2005

21. E. C. Sun and J. B. Kuo, “A Compact Threshold Voltage Model for Gate Misalignment Effect of DG FD SOI NMOS Devices Considering Fringing Electric Field Effects” , IEEE Transactions on Electron Devices , Vol. Vol. 51, No. 4 , pp 587-596-, Apr. 2004

22. E. C. Sun and J. B. Kuo, “A Compact Threshold Voltage Model for Gate Misalignment Effect of DG FD SOI NMOS Devices Considering Fringing Electric Field Effects” , IEEE Trans. Electron Devices , Vol. Vol. 51 , 587-596-, Apr. 2004

23. J. B. Kuo and S. C. Lin, “PD SOI-Technology SPICE Models” , Wiley's Texbook by J. B. Kuo: SOI CMOS VLSI Devices , Vol. ISBN 978-0471-464174 , pp. 377-400-, Apr. 2004

24. S. C. Lin and J. B. Kuo, “Modeling the Fringing Electric Field Effect on the Threshold Voltage of FD SOI NMOS Devices with the LDD/Sidewall Oxide Spacer Structure” , IEEE Transactions on Electron Devices , Vol. Vol. 50, No. 12 , pp. 2259-2264-, Dec. 2003

25. J. H. T. Chen and J. B. Kuo, “Ultra-low-voltage SOI CMOS Inverting Driver Circuit Using Effective Charge Pump Based on Bootstrap Technique” , Electronics Letters , Vol. Vol. 39, No. 2 , pp. 183-185-, Jan. 2003

26. J. H. T. Chen and J. B. Kuo, “Ultra-Low-Voltage SOI CMOS Inverting Driver Circuit Using Effective Charge Pump Based on Bootstrap Technique” , Electronics Letters , Vol. Vol. 39, No. 2 , pp.183-185-, Jan. 2003

27. S. C. Lin and J. B. Kuo, “Closed-Form Analytical Drain Current Model Considering Energy Transport and Self Heating for Short-Channel Fully-Depleted (FD) SOI NMOS Devices with Lightly-Doped Drain (LDD) Structure Biased in Strong Inversion” , IEEE Transactions on Electron Devices , Vol. Vol. 49, No. 12 , pp.2193-2203-, Dec. 2002

28. S. C. Lin and J. B. Kuo, “Closed-Form Breakdown Voltage Model for PD SOI NMOS Devices Considering Impact Ionization of Both Parasitic BJT and Surface MOS Channel Simultaneously” , IEEE Transactions on Electron Devices , Vol. Vol. 49, No. 11 , pp. 2016-2023-, Nov. 2002

29. Z. Zhang, H. H. Chen and J. B. Kuo, “0.8V CMOS Adiabatic Differential Switch Logic Circuit Using Bootstrap Technique for Low-Voltage Low-Power VLSI” , Electronics Letters , Vol. Vol. 38, No. 24 , pp. 1497-1499-, Nov. 2002

30. P. F. Lin and J. B. Kuo, “A 0.8-V 128-Kb Four-Way Set-Associative Two-Level CMOS Cache Memory Using Two-Stage Wordline/Bitline-Oriented Tag-Compare (WLOTC/BLOTC) Scheme” , IEEE Journal of Solid-State Circuits , Vol. Vol. 37, No. 10 , pp. 1307-1317-, Oct. 2002

31. P. C. Chen and J. B. Kuo, “Sub-1V CMOS Large Capacitive-Load Driver Circuit Using Direct Bootstrap Technique for Low-Voltage CMOS VLSI” , Electronics Letters , Vol. Vol. 38, No. 6 , pp. 265-267-, Mar. 2002

32. J. B. Kuo, K. H. Yuan, and S. C. Lin, “Compact Threshold-Voltage Model for Short-Chqannel Partially-Depleted (PD) SOI Dynamic-Threshold MOS (DTMOS) Devices” , IEEE Transactions on Electron Devices , Vol. Vol. 49, No. 1 , pp. 190-196-, Jan. 2002

33. P. F. Lin and J. B. Kuo, “A 1-V, 128-Kb Four-Way Set-Associative CMOS Cache Memory using Word-Line Oriented Tag-Compare (WLOTC) Structure with the Content-Addressable-Memory (CAM) 10-Transistor Tag Cell” , IEEE Journal of Solid-State Circuits , Vol. Vol. 36, No. 4 , pp. 666-675-, Apr. 2001

34. S. C. Liu, J. B. Kuo and Frank Wu, “A Novel Low-Voltage Content-Addressable-Memory (CAM) Cell with a Fast Tag-Compare Capability using Partially-Depleted (PD) SOI CMOS Dynamic-Threshold (DTMOS) Techniques” , IEEE Journal of Solid-State Circuits , Vol. Vol. 36, No. 4 , pp. 712-716-, Apr. 2001

35. Y. M. Huang and J. B. Kuo, “A High-Speed Conditional Carry Select (CCS) Adder Circuit with a Successively Incremented Carry Number Block (SICNB) Structure for Low-Voltage VLSI Implementation” , IEEE Transactions on Circuits and Systems--- II: Analog and Digital Signal Processing , Vol. Vol. 47, No.10 , pp. 1074 –1079-, Oct. 2000

36. S. C. Lin, J. B. Kuo, K. T. Huang and S. W. Sun, “A Closed-Form Back-Gate-Bias Related Inverse Narrow-Channel Effect Model for Deep-Submicron VLSI CMOS Devices Using Shallow Trench Isolation” , IEEE Transactions on Electron Devices , Vol. Vol. 47, No. 4 , pp. 725-733-, Apr. 2000

37. J. H. Lou and J. B. Kuo, “A 1.5V CMOS All-N-Logic True-Single-Phase (TSP) Bootstrapped Dynamic Logic (BDL) Circuit Suitable for Low Supply Voltage and High Speed Pipelined System Operation” , IEEE Transactions on Circuits and Systems---II: Analog and Digital Signal Processing , Vol. Vol. 46, No. 5 , pp 628-631-, May 1999

38. S. C Lin and J. B. Kuo, “Temperature-Dependent Kink Effect Model for Partially-Depleted SOI NMOS Devices” , IEEE Transactions on Electron Devices , Vol. Vol. 46, No. 1 , pp. 254-258-, Jan. 1999

39. J. B. Kuo, “Bandgap Narrowing” , Wiley Encyclopedia on Electrical Engineering , Jan. 1999

40. P. F. Lin and J. B. Kuo, “A CMOS Semi-Static Latch Circuit without Charge Sharing and Leakage Current Problems” , in Low-Voltage CMOS VLSI Circuits, John Wiley: New York , pp.167-171-, Jan. 1999

41. J. H. Lou and J. B. Kuo, “A Low-Voltage Semi-Dynamic DCVSPG-Domino Logic Circuit” , in Low-Voltage CMOS VLSI Circuits, John Wiley: New York , pp. 225-228-, Jan. 1999

42. J. B. Kuo, “Modeling of Deep-Submicron SOI CMOS VLSI Devices” , National Science Council Monthly , Jan. 1999

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Conference & proceeding papers:

1. C. Hong, L. Yang, Q. Cheng, T. Han, J. B. Kuo and Y. Chen, “A Nonlinear Surface-Field Compact Model for Juinctionless Nanowire MOSFET” , Workshop on Microelectronics and Electron Devices (WMED) , Boise, USA , Apr. 2016

2. S. K. Hu and J. B. Kuo, “Analysis of Subthreshold Behavior of SOI NMOS De ice Considering Back-Gate-Bias-Related Flaoting Body Effect” , Workshop on Microelectronics and Electron Devices (WMED), Boise, USA , Boise, USA , Mar. 2015

3. S. K. Hu, J. B. Kuo and Y. J. Chen, “Floating-Body-Efffect-Correlated Subthreshold Behavior of SOI NMOS Device Considering Back-Gate-Bias Effect” , Spanish Conference on Electron Devices , Aranjuez, Spain , Jan. 2015

4. C. B. Hsu, Y. S. Hong and J. B. Kuo, “MTCMOS Low-Power Optimization Technique (LPOT) for 1V Pipelined RISC CPU Circuit” , ICECS , Marseille, France , Dec. 2014

5. C. B. Hsu and J. B. Kuo, “MTCMOS Low-Power Design Technique (LPDT) for Low-Voltage Piepelined Mcoprocessor Circuit” , ISIC , Singapore , Dec. 2014

6. D. H. Lung, S. K. Hu, J. B. Kuo, D. Chen, “Parasitic BJT versus DIBL: Floating-Body-Related Subthreshold Characteristics of SOI NMOS Device” , ISIC , Singapore , Dec. 2014

7. S. K. Hu, D. H. Lung, J. B. Kuo and D. Chen, “Back-Gate-Baias Induced Floating-Body-Related Subthreshold Characteristics of SOI NMOS Device” , IEDMS , Hualien, Taiwan , Nov. 2014

8. J. B. Kuo, “Compact Modeling of 40nm Pd SOI NMOS Devices Considering Floating Body Effect” , MOST Microelectronics Research Seminar , Hualien, Taiwan , Nov. 2014

9. G. Lin and J. B. Kuo, “Critical-Path Aware Power Consumption Optimization Methodology (CPAPCOM) Using Mixed-Vth Cells for Low-Power SOC Designs” , ISCAS , Melbourne, Australia , Jun. 2014

10. C. B. Hsu and J. B. Kuo, “Power Consumption Optimization Methodology (PCOM) for Low-Power/Low-Voltage 32-bit Microprocessor Circuit Design via MTCMOS” , MWSCAS , College Station, Texas , Aug. 2014

11. D. H. Lung and J. B. Kuo, “Subthreshold Behavior of the SOI NMOS Device Consdiering BJT and DIBL Effects” , EUROSOI , Tarragona, Barcelona, Spain , Jan. 2014

12. G. Lin, C. B. Hsu and J. B. Kuo, “Leakage Power Consumption Reduction Strategy (PCRS) Using Mixed-Vth (MVT) Cells for Low-Voltage/Low-Power SOC” , Asia Pacific CSEE Conference , Seoul, Korea , Jan. 2014

13. D. H. Lung and J. B. Kuo, “Back-Gate Bias Effect of PD SOI NMOS Device Considering BJT” , International Conference on EECS , Hong Kong , Dec. 2013

14. D. H. Lung, J. B. Kuo and D. Chen, “Turn-on Transient Behavior of PD SOI NMOS Device Considering the Back-Gate Bias Effect” , International Semiconductor Devices Research Symposium , Bethesda, MD, USA , Dec. 2013

15. D. H. Lung, J. B. Kuo and D. Chen, “Turn-off Transient Behavior of PD SOI NMOS Device Considering the Back-Gate Bias Effect” , International Electron Devices and Material Symposium , Nantou, Taiwan , Nov. 2013

16. J. B. Kuo, “Modeling Advanced PD SOI CMOS Devices” , NSC Seminar , Nantou, Taiwan , Nov. 2013

17. G. Lin and J. B. Kuo, “Novel Power Consumption Reduction strategy Using Mixed-Vth Cells for Optimizaing the Cells on Critical Paths for Low-Power SOC” , International Conference on EECS , Beijing, China , May 2013

18. A. P. Chuang, S. I. Su, Z. H. Yang, J. B. Kuo, D. Chen and C. S. Yeh, “Function of the Upper/Lower Parasitic BJTs in 40nm PD SOI NMOS Device due to the Back-Gate Bias Effect” , EUROSOI , Paris, France , Jan. 2013

19. T. C. Liu, J. B. Kuo and S. Zhang, “Grain-Boundary Impact Ionization-Induced Current Hump Effects of Polysilicon TFTs” , IEDMS , Kaohsiung , Nov. 2012

20. J. B. Kuo, “Compact Modeling of SOI CMOS Devices” , NSC Seminar , Kaohsiung , Nov. 2012

21. T. C. Liu, J. B. Kuo and S. D. Zhang, “Design of Distortionless Interconnects via Main/auxiliary Structure with LC Line for High Speed On-chip Transmission” , ICSICT , Xian, China , Oct. 2012

22. S. W. Fang, J. B. Kuo, D. Chen and C. S. Yeh, “Turn-off Transient Behavior of 40nm PD SOI NMOS Device Considering the Floating Body Effect” , Eurosoi Conference , Montpellier, France , Jan. 2012

23. T. C. Liu, J. B. Kuo and S. D. Zhang, “Floating-Body Kink Effect: Ply-Si TFT versus SOI CMOS” , Eurosoi Conference , Montpellier, France , Jan. 2012

24. T. C. Liu and J. B. Kuo, “Grain Boundary-Related Kink Effects of Poly-Si TFTs” , EDSSC , Bangkok, Thailand , Dec. 2012

25. L. L. Wang, J. B. Kuo, S. Zhang, “Modeling Hot-Carrier-Induced Reliability of Poly-silicon Thin Film Transistors” , EDSSC , Bangkok, Thailand , Dec. 2012

26. J. B. Kuo, “Evolution of SOI CMOS Devices and Circuits for Low0Power/ Low Vltage SOC Applications” , Electron Devices Innovation Symposium , Osaka Japan , Dec. 2011

27. S. W. Fang, J. B. Kuo, D. Chen and C. S. Yeh, “Modeling the Floating-Body-Effect-Related Transient Behavior of 40nm PD SOI NMOS Device via the SPICE Bipolar/MOS Model” , International Semiconductor Device Research Symposium ISDRS , College Park, Maryland , Dec. 2011

28. J. B. Kuo, “Compact Modeling of Nanometer SOI CMOS Devices Considering Shallow Trench Isolation” , NSC Seminar , Taipei , Nov. 2011

29. S. F. Huang, R. S. Shen, and J. B. Kuo, “Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications using MTCMOS Techniques” , Power and Timing Modeling Optimization Symposium , Madrid, Spain , Nov. 2011

30. C. H. Chen, J. B. Kuo, D. Chen, and C. S. Yeh, “Analysis of Turn-off Transient Behavior of the 40nm PD SOI NMOS Device with the Floating Body Effect” , International Electron Device Material Symposium , Taipei , Nov. 2011

31. C. H. Chen, J. B. Kuo, D. Chen, and C. S. Yeh, “Analysis of Turn-off Transient Behavior of the 40nm PD SOI NMOS Device with the Floating Body Effect” , Eurosoi Conference , Grenada, Spain , Jan. 2011

32. C. H. Chen, J. B. Kuo, D. Chen and C. S. Yeh, “Modeling the Bipolar Device in the 40nm PD SOI NMOS Device Considering the Floating Body Effect” , ICSICT , Shanghai , Nov. 2010

33. C. F. Yen and J. B. Kuo, “Charge Pumping Behavior of STI-Isolated PD SOI NMOS Device Operating at Low Temp” , IEDMS , Chungli, Taiwan , Nov. 2010

34. W.C.H. Lin and J. B. Kuo, “Low-Voltage SOI CMOS DTMOS/MTCMOS Circuit Technique for Design Optimization of Low-power SOC Applications” , ISCAS , Paris , Jun. 2010

35. J. S. Su, J. B. Kuo, D. Chen and C. S. Yeh, “Modeling the Floating-Body-Effect-Induced Drain Current Behavior of 40nm PD SOI NMOS Device Via SPICE BJT/MOS Model Approach” , EUROSOI , Grenoble, France , Jan. 2010

36. H. J. Hung, J. B. Kuo, C. T. Tsai and D. Chen, “Floating-Body-Effect-Related Gate Tunneling Leakage Current Phenomenon of 40nm PD SOI NMOS Device” , International Semiconductor Devices Research Symposium , Washington, DC , Dec. 2009

37. H. J. Hung, J. B. Kuo, D. Chen and C. S. Yeh, “Gate Tunneling Leakage Current Behavior of 40nm PD SOI NMOS Device Considerign the Floating Body Effect” , International Electron Devices Materials Symposium , Taiwan , Nov. 2009

38. J. B. Kuo, “Compact Modelign of Nanometer SOI CMOS Devices Considering Shallow Trench Isolation” , NSC Seminar , Taiwan , Nov. 2009

39. C. H. Lin and J. B. Kuo, “Design Optimization of Low-Power 90nm CMOS SOC Applications Using 0.5V Bulk PMOS Dynamic-Threshold with Dual Threshold (MTCMOS) BP-DTMOS-DT Technique” , Power and Timing Optimization Symposium , Delft, Netherlands , Sep. 2009

40. J. S. Su and J. B. Kuo, “Modeling the Floating-Body-Effect-Induced Drain Current Behavior of PD SOI NMOS Device Via SPICE BJT/MOS Model Approach” , Compact TFT Modeling Workshop , London , Sep. 2009

41. J. I. Lu, H. J. Hung, J. B. Kuo, D. Chen, C. S. Yeh and C. T. Tsai, “Shallow Trench Isolated-Related Narrow Channel Effect on Kink Effect and Breakdown Behavior of 40nm PD SOI NMOS Device” , EUROSOI , Gothenburg, Sweden , Jan. 2009

42. H. J. Hung, J. I. Lu, J. B. Kuo, D. Chen and C. S. Yeh, “Floating-Body-Effect-Related Gate Tunneling Leakage Current Behavior of 40nm PD SOI NMOS Device” , EUROSOI , Gothenburg, Sweden , Jan. 2009

43. W. J. H. Lin, C. Y. Chien and J. B. Kuo, “0.5V SOI CMOS Dual-Threshold Circuit Technique Via DTMOS for Design Optimization of Low-Power VLSI System Applications” , EUROSOI , Gothenburg , Jan. 2009

44. J. B. Kuo, “Analysis of STI Mechanical-Stress Induced Effects on 40nm PD SOI NMOS Devices” , IEDMS , Taichung , Nov. 2008

45. J. S. Su and J. B. Kuo, “Transient Behavior of 40nm PD SOI NMOS Device Considering STI-Induced Mechanical Stress Effects” , IEDMS , Taichung , Nov. 2008

46. H. J. Hung, J. I. Lu, J. B. Kuo, G. S. Lin, C. S. Yeh, C. T. Tsai and M. Ma, “STI Mechanical-Stress Induced Small-Geometry Effect on Hysteresis Phenomenon of 40nm PD SOI NMOS Device” , IEDMS , Taichung , Nov. 2008

47. J. B. Kuo, “Compact Modeling of Sub-90nm CMOS VLSI Devices Considering Fringing Electric Field Effects” , NSC Seminar , Taichung , Nov. 2008

48. J. B. Kuo, D. Chen, C. S. Yeh, C. T. Tsai and M. Ma, “STI-Induced Mechanical Stress-Related Breakdown Behavior of 40nm PD SOI NMOS Devices” , ICSICT , Beijing , Oct. 2008

49. R. Chen, R. Liu and J. B. Kuo, “Gate-Level Dual-Threshold Total Power Optimization Methodology (GDTPOM) Principle for Designing High-Speed Low-Power SOC Applications” , ICSICT , Beijing , Oct. 2008

50. J. B. Kuo, “Analysis of STI Mechanical-Stress Induced Effects of Nanometer PD SOI NMOS Devices” , SRC Conference , Gainesville, FL, USA , May 2008

51. I. S. Lin, V. C. Su, J. B. Kuo, D. Chen, C. S. Yeh, C. T. Tsai, and M. Ma, “STI-Induced Mechanical-Stress-Related Kink Effect of 40nm PD SOI NMOS Devices” , European SOI Conference , Cork, Ireland , Jan. 2008

52. I. Lin, V. Su, J. B. kuo, M. Ma, C. T. Tsai, C. S. Yeh and D. Chen, “STI Mechanical Stress Induced Subthreshold Kink Effect of 40nm PD SOI NMOS Devices” , IEEE International Semicondcutor Device Research Symp (ISDRS) , College Park, Maryland , Dec. 2007

53. I. Lin, V. Su, J. Kuo, R. Lee, G. Lin, D. Chen, C. Yeh, C. Tsai and M. Ma, “Influence of STI-Induced Mechanical Stress in Kink Effect of 65nm PD SOI CMOS Devices” , Electron Devices and Solid State State Circuits (EDSSC) Conf , Tainan, Taiwan , Dec. 2007

54. C. H. Hsu and J. B. Kuo, “Modeling the Drain Current of DG FD SOI NMOS Devices with N+/P+ Top/Bottom Gate” , Electron Devices and Solid State State Circuits (EDSSC) Conf , Tainan, Taiwan , Dec. 2007

55. H. Chen, J. B. Kuo and M. Syrzycki, “Triple Threshold Static Power Minimization in High-Level Synthesis of VLSI CMOS” , Power and Timing Modeling and Optimization Conf (PATMOS) , Gothenburg, Sweden , Sep. 2007

56. J. B. Kuo, “Modeling the Gate Tunneling Current Effects of Sub-100nm NMO” , International Electron devices Semiconductor Technology Conf (IEDST) , Beijing, China , Jun. 2007

57. H. I. Chen, E. K. Loo, J. B. Kuo and M. J. Syrzycki, “Triple-Threshold Static Power Minimization Technique in High-Level Synthesis for Designing High-Speed Lower-Power Applications using 90nm MTCMOS Technology” , CCECE , Vancouver, Canada , Apr. 2007

58. H. Lin, J. Kuo, r. Sobot and M. Syrzycki, “Investigation of Substrate Noise Isolation Solutions in Deep Submicron CMOS Technology” , CCECE , Vancouver, Canada , Apr. 2007

59. E. K. Loo, J. B. Kuo and M. Syrzycki, “Low-Voltage Single-Phase Clocking Adiabatic DCVS Logic Circuit with Pass Gate Logic” , CCECE , Vancouver, Canada , Apr. 2007

60. C. H. Lin, J. B. Kuo, K. W. Su and S. Liu, “Compact Gate Tunneling Current Model Considering Distributed Effect for Sub-100nm NMOS Devices with Ultra-thin (1nm) Gate Oxide” , IEDMS , Tainan, Taiwan , Dec. 2006

61. C. C. Chen, J. B. Kuo, K. W. Su, and S. Liu, “Analysis of Fringing Electric Field Related Capacitance Behavior of Narrow-Channel FD SOI NMOS Devices Using 3D Simulation” , ICSICT , Shanghai, China , Oct. 2006

62. B. Chung and J. B. Kuo, “Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) Using Path-Based Static Timing Analysis (STA) Technique” , PATMOS , Montpellier, France , Sep. 2006

63. B. Chung and J. B. Kuo, “Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology” , ISCAS , Greece , May 2006

64. J. B. Kuo, “Capacitance Behavior of Nanometer FD SOI CMOS Devices with HfO2 High-k Gate Dielectric Considering Gate Tunneling Leakage Current” , MIEL , Europe , May 2006

65. J. B. Kuo, “Fringing Effects of Nanometer SOI CMOS Devices” , NIEL , Nis, Serbia , May 2006

66. J. B. Kuo, “Capacitance Behavior of Nanometer FD SOI CMOS Devices with HfO2 High-k Gate Dielectric Considering Gate Tunneling Leakage Current” , MIEL , Europe , May 2006

67. B. Chung and J. B. Kuo, “Gate-Level Dual-Threshold Static Power Optimization Methodology (GDSPOM) for Designing High-Speed Low-Power SOC Applications Using 90nm MTCMOS Technology” , ISCAS , Greece , May 2006

68. Y. S. Lin, C. H. Lin, J. B. Kuo and K. W. Su, “CGS Capacitance Phenomenon of 100nm FD SOI CMOS Devices with HfO2 High-k Gate Dielectric Considering Vertical and Fringing Displacement Effects” , HKEDSSC , Hong Kong , Dec. 2005

69. J. B. KUo, C. H. Hsu and C. P. Yang, “Gate-Misalignment Related Capacitance Behavior of a 100nm DG SOI MOS Devices with N+/p+ Top/Bottom Gate” , HKEDSSC , Hong Kong , Dec. 2005

70. G. S. Lin and J. B. Kuo, “Floating-Body Kink-Effect RElated Capacitance Behavior of Nanometer PD SOI NMOS Devices” , EDMS , Taiwan , Oct. 2005

71. G. S. Lin and J. B. Kuo, “Fringing-Induced Narrow-Channel-Effect (FINCE) RElated Capacitance Behavior of Nanometer FD SOI NMOS Devices Using Mesa-Isolation Via 3D Simulation” , EDSM , Taiwan , Oct. 2005

72. J. B. Kuo, “Evolution of Bootstrap Techniques in Low-Voltage CMOS Digital VLSI Circuits for SOC Applications” , IWSOC , Banff, Canada , Jul. 2005

73. G. Y. Liu, N. C. Wang and J. B. Kuo, “Energy-Efficient CMOS Large-Load Driver Circuit with the Complementary Adiabatic/Bootstrap (CAB) Technique for Low-Power TFT-LCD System Applications” , ISCAS , Kobe, Japan , May 2005

74. Y. S. Lin, C. H. Lin, J. B. Kuo and K. W. Su, “CGS Capacitance Phenomenon of 100nm FD SOI CMOS Devices with HfO2 High-k Gate Dielectric Considering Vertical and Fringing Displacement Effects” , HKEDSSC , Hong Kong , Dec. 2005

75. J. B. KUo, C. H. Hsu and C. P. Yang, “Gate-Misalignment Related Capacitance Behavior of a 100nm DG SOI MOS Devices with N+/p+ Top/Bottom Gate” , HKEDSSC , Hong Kong , Dec. 2005

76. G. Y. Liu, N. C. Wang and J. B. Kuo, “Energy-Efficient CMOS Large-Load Driver Circuit with the Complementary Adiabatic/Bootstrap (CAB) Technique for Low-Power TFT-LCD System Applications” , ISCAS , Kobe, Japan , May 2005

77. H. P. Chen and J. B. Kuo, “A 0.8V CMOS TSPC Adiabatic DCVS Logic Circuit with the Bootstrap Technique for Low-Power VLSI” , ICECS , Israel , Dec. 2004

78. J. B. Kuo, C. H. Hsu and C. P. Yang, “Gate Misalignment Effect Related Capacitance Behavior of a 100nm DG FD SOI NMOS Device with n+/p+ Poly Top/Bottom Gate” , ICSICT , Beijing, China , Oct. 2004

79. J. B. Kuo, “Gate Misalignment Effects of DG SOI NMOS Devices” , VLSI/CAD Conference , Taipei , Aug. 2004

80. J. B. Kuo and H. P. Chen, “A Low-Voltage CMOS Load Driver with the Adiabatic and Bootstrap Techniques for Low-Power System Applications” , MWSCAS , Hiroshima, Japan , Jul. 2004

81. J. B. Kuo, “Trends on CMOS VLSI” , International Meeting on Nanotechnology , Singapore , Jul. 2004

82. J. B. Kuo, “Evolution of Low-Voltage CMOS Digital Circuits Using Bootstrap Techniques” , IMFEDK , Kyoto, Japan , Jul. 2004

83. M. T. Lin, E. C. Sun, and J. B. Kuo, “Asymmetric Gate Misalignment Effect on Subthreshold Characteristics DG SOI NMOS Devices Considering Fringing Electric Field Effect” , Electron Devices and Material Symposium , Dec. 2003

84. J. B. Kuo, E. C. Sun, and M. T. Lin, “Analysis of Gate Misalignment Effect on the Threshold Voltage of Double-Gate (DG) Ultrathin FD SOI NMOS Devices Using a Compact Model Considering Fringing Electric Field Effect” , IEEE Electron Devices for Microwave and Optoelectronic Applications , Nov. 2003

85. J. .B. Kuo, “Compact Modeling of SOI CMOS VLSI Devices” , NSC Research Seminar , Taipei , Nov. 2003

86. E. Shen and J. B. Kuo, “A Novel 0.8V BP-DTMOS Content Addressable Memory Cell Circuit Derived from SOI-DTMOS Techniques” , IEEE Conference on Electron Devices and Solid State Circuits , Hong Kong , Jul. 2003

87. P. C. Chen and J. B. Kuo, “Novel Sub-1V CMOS Domino Dynamic Logic Circuit Using a Direct Bootstrap (DB) Technique for Low-voltage CMOS VLSI” , International Symposium on Circuits and Systems , May 2003

88. J. B. Kuo, “SOI CMOS VLSI” , Fellow Series Meeting , Hsin-Chu, Taiwan , Mar. 2003

89. J. B. Kuo and S. C. Lin, “Compact Breakdown Model for PD SOI NMOS Devices Considering BJT/MOS Impact Ionization for SPICE Circuits Simulation” , IEDMS , Taipei , Dec. 2002

90. J. B. Kuo and S. C. Lin, “Compact LDD/FD SOI CMOS Device Model Considering Energy Transport and Self Heating for SPICE Circuit Simulation” , IEDMS , Taipei , Dec. 2002

91. S. C. Lin and J. B. Kuo, “Fringing-Induced Barrier Lowering (FIBL) Effects of 100nm FD SOI NMOS Devices with High Permittivity Gate Dielectrics and LDD/Sidewall Oxide Spacer” , IEEE SOI Conference Proc , Williamsburg , Oct. 2002

92. J. B. Kuo and S. C. Lin, “The Fringing Electric Field Effect on the Short-Channel Effect Threshold Voltage of FD SOI NMOS Devices with LDD/Sidewall Oxide Spacer Structure” , Hong Kong Electron Devices Meeting , Jun. 2002

93. C. L. Yang and J. B. Kuo, “High-Temperature Quasi-Saturation Model of High-Voltage DMOS Power Devices” , Hong Kong Electron Devices Meeting , Jun. 2002

94. E. Shen and J. B. Kuo, “0.8V CMOS Content-Addressable-Memory (CAM) Cell Ciurcuit with a Fast Tag-Compare Capability Using Bulk PMOS Dynamic-Threshold (BP-DTMOS) Technique Based on Standard CMOS Technology for Low-Voltage VLSI Systems” , International Symposium on Circuits and Systems (ISCAS) Proceedings , Arizona , May 2002

95. J. B. Kuo and S. C. Lin, “Modeling of Single-Transistor Latch Behavior in Partially-Depleted (PD) SOI CMOS Devices Using a Concise SOI-SPICE Model” , International Conference on Semiconductor IC Technology (ICSICT) , Shanghai , Oct. 2001

96. J. B. Kuo and T. Y. Chiang, “Novel 0.8V True-Single-Phase-Clocking (TSPC) Latches Using PD-SOI DTMOS Techniques for Low-Voltage CMOS VLSI Circuits” , IEEE SOI Conference Proceedings , Colorado , Oct. 2001

97. J. B. Kuo and P. F. Lin, “A 0.8V 0.77mW at 50MHz 128Kb Four-Way Set-Associative 2-Level CMOS Cache Memory Using Two-Stage WLOTC/BLOTC Tag-Compare Scheme and Sense Wordline/Bitlines (SWL/SBL) Tag Sense Amps with an 8-T Tag Cell in Level 2 and a 10-T Shrunk Logic Swing (SLS) Memory” , European Solid-State Circuits Conference (ESSCIRC) , Villach, Austria , Sep. 2001

98. J. B. Kuo, “Future Trends on SOI CMOS VLSI” , Canadian Semiconductor Technology Conference , Ottawa , Aug. 2001

99. J. B. Kuo, P. F. Lin, F. Wang, H. H. Chang, W. T. Wang, and C. H. Chen, “A 1-V, 3.44-ns, 4.1-mW at 50-MHz, 128-Kb Four-Way Set-Associative CMOS Cache Memory Implemented by 1.8V 0.18um Foundry CMOS Technology for Low-Voltage Low-Power VLSI System Applications” , 26th European Solid-State Circuits Conference (ESSCIRC) , Stockholm , Sep. 2000

100. B. T. Wang and J. B. Kuo, “A Novel Low-Voltage Silicon-On-Insulator (SOI) CMOS Complementary Pass-Transistor Logic (CPL) Circuit using Asymmetrical Dynamic Threshold Pass-Transistor (ADTPT) Technique” , IEEE 43rd Midwest symposium on Circuits and Systems (MWSCAS) , Aug. 2000

101. J. B. Kuo, “SPICE Compact Modeling of PD-SOI CMOS Devices” , Keynote Speech of IEEE Hong Kong Electron Devices Meeting (HKEDM) , Hong Kong , Jun. 2000

102. S. C. Lin, K. H. Yuan and J. B. Kuo, “Short-Channel Effects of SOI Partially-Depleted (PD) Dynamic-Threshold MOS (DTMOS) Devices” , IEEE Hong Kong Electron Devices Meeting (HKEDM) , Hong Kong , Jun. 2000

103. B. T. Wang and J. B. Kuo, “A Novel Two-Port 6T CMOS SRAM Cell Structure for Low-Voltage VLSI SRAM with Single-Bit-Line Simultaneous Read-and-Write Access (SBLSRWA) Capability” , IEEE International Symposium on Circuits and Systems (ISCAS) , Geneva , May 2000

104. S. C. Liu and J. B. Kuo, “A Novel 0.7V Two-Port 6T SRAM Memory Cell Structure with Single-Bit-Line Simultaneous Read-and-Write Access (SBLSRWA) Capability using Partially Depleted SOI Dynamic-Threshold Technique” , IEEE International SOI Conference Proceedings , Oct. 1999

105. J. B. Kuo, “Semiconductor R&D in Taiwan” , Association of East Asian Research Universities 1st Microelectronics Workshop , Oct. 1999

106. J. B. Kuo, K. W. Su, and S. C. Lin, “Compact MOS/Bipolar Charge-Control Model of Partially-Depleted SOI CMOS Devices for VLSI Circuit Simulation---SOI-Technology (ST)-SPICE” , European Solid State Device Research Conference (ESSDERC) , Belgium , Sep. 1999

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Books:

1. J. B. Kuo and S. C. Lin, “Low-Voltage SOI CMOS VLSI Devices and Circuits” , Wiley Interscience, New York , 440pages , USA, Apr. 2004

2. J. B. Kuo, “CMOS Digital IC” , Chuan-Hwa Publisher , Taipei, Mar. 2004

3. J. B. Kuo and S. C. Lin, “Low-Voltage SOI CMOS VLSI Devices and Circuits” , John Wiley , 407 pages , New York, Sep. 2001

4. J. B. Kuo and J. H. Lou, “Low-Voltage CMOS VLSI Circuits” , John Wiley , 450 pages , New York, Jan. 1999

5. J. B. Kuo and K. W. Su, “CMOS VLSI Engineering: Silicon-on-Insulator (SOI)” , Kluwer Academic Publishers , 460 pages , Netherlands, Sep. 1998

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Patents:

1. J. B. Kuo and S. C. Liu, “Low-Voltage Content Addressable Memory Cell with a Fast Tag-Compare Capability Using Partially-Depleted SOI CMOS Dynamic-Threshold Techniques” , US Patent No. 6240004, May 2001

2. J. B. Kuo and S. C. Liu, “0.7V Two-Port 6T SRAM Cell Structure with Single-Bit-Line Simultaneous Read-and-Write Access (SBLSRWA) Capability using Partially-Depleted SOI CMOS Dynamic-Threshold Techniques” , US Patent No. 6061268, May 2000

3. J. B. Kuo and B. T. Wang, “Two-Port 6T CMOS SRAM Cell Structure for Low-Voltage VLSI SRAM with Single-Bit-Line Simultaneous Read-and Write Access (SBLSRWA) Capability” , US patent No. 6118689, Jan. 2000

4. J. B. Kuo and J. H. Lou, “A 1.5V Bootstrapped Pass-Transistor-Based Carry Look-Ahead Circuit suitable for Low-Voltage CMOS VLSI” , US patent No. 5898333, Apr. 1999

5. J. B. Kuo and J. H. Lou, “A 1.5V Bootstrapped All-N-Logic True-Single-Phase CMOS Dynamic Logic Circuit suitable for Low Supply Voltage and High Speed Pipelined System Operation” , US patent No. 5973514, Jan. 1999

6. J. B. Kuo and B. T. Wang, “A Novel Low-Voltage Silicon-On-Insulator (SOI) CMOS Complementary Pass-Transistor Logic (CPL) Circuit using Asymmetrical Dynamic Threshold Pass-Transistor (ADTPT) Technique” , US Patent granted in Sept 2000, Jan. 0

7. J. B. Kuo, “A Charge-Sharing-Problem-Free 1.5V BiCMOS Dynamic Logic Gate Circuit” , ROC Patent approved in 1999, Jan. 0

8. J. B. Kuo and J. H. Lou, “A High-Speed 1.5V Clocked BiCMOS Latch for BiCMOS Dynamic Pipelined Digital Logic VLSI Systems” , ROC Patent approved in 1999, Jan. 0

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