李致毅 Lee, Jri
- Professor, Department of Electrical Engineering, National Taiwan University
- Ph.D. UCLA, 2003
- M.S. UCLA, 2003
- B.S. National Taiwan University, 1995
- Office : EE2 309
- TEL : +886-2-33663583
- FAX : +886-2-2368-1679
- Email :
- Office Hour :
- Website : http://cc.ee.ntu.edu.tw/~jrilee/
Major Research Areas
Ultrawide Band (UWB) Transceivers, Optical Communication Circuits, Phase-Locked Loops, and Data Converers.
Research Summary
Dr. Lee's research interests include broadband data communication circuits, wireless transceivers, phase-locked loops and low-noise broadband amplification, A/D and D/A converters, and modeling of passive and active devices in deep-submicron CMOS technologies.
Jri Lee (M’ 03) received the B.Sc. degree in electrical engineering from National Taiwan University, Taipei, Taiwan, in 1995, and the M.S. and Ph.D. degrees in electrical engineering from the University of California, Los Angeles (UCLA), both in 2003.
From 1997 to 1998, he was with Academia Sinica, Taipei, Taiwan, investigating control systems for novel solid-state lasers. From 2000 to 2001, he was with Cognet Microsystems, Los Angeles, CA, and subsequently with Intel Corporation, where he worked on SONET OC-192 and OC-48 transceivers. Since 2004, he has been Assistant Professor of electrical engineering at National Taiwan University. He is currently serving on the Technical Program Committees of the International Solid-State Circuits Conference (ISSCC) and Asian Solid-State Circuits Conference (A-SSCC). His research interests include broadband data communication circuits, wireless transceivers, A/D and D/A converters, phase-locked loops and low-noise broadband amplification, and modeling of passive and active devices in deep-submicron and nanometer CMOS technologies.
Journal articles & book chapters
1. Jri Lee, M. Chen, and H. Wang, “Design and Comparison of Three 20-Gb/s Backplane Transceivers for Duobinary” , IEEE Journal of Solid-State Circuits , Vol. vol. 43 , pp. 2120-2133-, Sep. 2008
2. Jri Lee, M. Liu, and H. Wang, “A 75-GHz Phase-Locked Loop in 90-nm CMOS Technique” , IEEE Journal of Solid-State Circuits , Vol. vol. 43 , pp. 1414-1426-, Jun. 2008
3. Jri Lee and M. Liu, “A 20-Gb/s Burst-Mode Clock and Data Recovery Circuit Using Injection-Locking Technique” , IEEE Journal of Solid-State Circuits , Vol. vol. 43 , pp. 619-630-, Mar. 2008
4. Jri Lee, “A 20-Gb/s Adaptive Equalizer in 0.13 um CMOS Technology” , IEEE Journal of Solid-State Circuits , Vol. vol. 41 , pp. 2058-2066-, Sep. 2006
5. Jri Lee, “High-Speed Circuit Designs for Transmitters in Broadband Data Links” , IEEE Journal of Solid-State Circuits , Vol. vol. 41 , pp. 1004-1015-, May 2006
6. Jri Lee, “A 3-to-8-GHz Fast Hopping Frequency Synthesizer in 0.18-um CMOS Technology” , IEEE Journal of Solid-State Circuits , Vol. vol. 41 , pp. 566-573-, Mar. 2006
7. Jri Lee, Ken Kundert and Behzad Razavi, “Analysis and Modeling of Bang-Bang Clock and Data Recovery Circuits” , IEEE Journal of Solid-State Circuits , Vol. vol. 39 , pp. 1571-1580-, Sep. 2004
8. Jri Lee and Behzad Razavi, “A 40-GHz Frequency Divider in 0.18-um CMOS Technology” , IEEE Journal of Solid-State Circuits , Vol. vol. 39 , pp. 594-601-, Apr. 2004
9. Jri Lee and Behzad Razavi, “A 40-Gb/s Clock and Data Recovery Circuit in 0.18-um CMOS Technology” , IEEE Journal of Solid-State Circuits , Vol. vol. 38 , pp. 2181-2190-, Dec. 2003
Conference & proceeding papers:
1. Jri Lee, M. Chen, and H. Wang, “A 20-Gb/s Duobinary Transceiver in 90-nm CMOS” , International Solid-State Circuits Conference , San Francisco , Feb. 2008
2. Jri Lee and M. Liu, “A 20-Gb/s Burst-Mode CDR in 90-nm CMOS” , International Solid-State Circuits Conference , San Francisco , Feb. 2007
3. Jri Lee, “A 75GHz PLL in 90nmCMOS” , nternational Solid-State Circuits Conference , San Francisco , Feb. 2007
4. Jri Lee and Huaide Wang, “A 20-Gb/s Broadband Transmitter with Auto-Configuration Technique” , nternational Solid-State Circuits Conference , San Francisco , Feb. 2007
5. Jri Lee, “A 20-Gb/s Adaptive Equalizer in 0.13-um CMOS Technology” , International Solid-State Circuits Conference , Feb. 2006
6. Jri Lee, Jian-yu Ding, Tuan-yi Cheng, “A 20-Gb/s 2-to-1MUX and a 40-GHz VCO in 0.18-um CMOS Technology” , Symposium on VLSI Circuits , Tyoto, Japan , Jun. 2005
7. Jri Lee and Shanghann Wu, “Design and Analysis of a 20-GHz Clock Multiplication Unit in 0.18-um CMOS Technology” , Symposium on VLSI Circuits , Tyoto, Japan , Jun. 2005
8. Jri Lee and Da-wei Chiu, “A 7-Band 3-8 GHz Frequency Synthesizer with 1-ns Band-Switching Time in 0.18-um CMOS Technology” , International Solid-State Circuits Conference , San Francisco , Feb. 2005
9. SriKanth Gondi, Jri Lee and Behzad Razavi,, “A 10-Gb/s CMOS Adaptive Equalizer for Backplane Applications” , International Solid-State Circuits Conference , San Francisco , Feb. 2005
10. Jri Lee, Ken Kundert and Behzad Razavi, “Modeling of Jitter in Bang-Bang Clock and Data Recovery Circuits” , Custom Integrated Circuits Conference , San Jose , Sep. 2003
11. Jri Lee and Behzad Razavi, “A 40-GHz Frequency Divider in 0.18-um CMOS Technology” , Symposium on VLSI Circuits , Tyoto, Japan , Jun. 2003
12. Jri Lee and Behzad Razavi, “A 40-Gb/s Clock and Data Recovery Circuit in 0.18-um CMOS Technology” , International Solid-State Circuits Conference , San Francisco , Feb. 2003
Books:
1. Jri Lee, “mm-Wave Silicon Technology: 60GHz and Beyond (Chapter 5: Voltage-Controlled Oscillators and Frequency Dividers)” , Springer , USA, Feb. 2008
Patents:
1. Jri Lee and Behzad Razavi, “High-speed clock and data recovery circuit” , U.S. Patent No. 7,286,625, Jan. 2007
2. Andrew Kung, Jri Lee, “Efficient frequency conversion apparatus for use with nultimode solid-state lasers” , U.S. Patent No. 6,005,878, Jan. 1998