李泰成 Lee, Tai-Cheng
- Professor, Department of Electrical Engineering, National Taiwan University
- Ph.D. EE, University of California at Los Angeles, 2001
- M.S. EE, Stanford University, 1994
- B.S. EE, National Taiwan University , 1992
- Office : EE2 445
- TEL : +886-2-33663645
- FAX : +886-2-23681679
- Email :
- Office Hour : Mon. 10am~12pm
- Website : http://cc.ee.ntu.edu.tw/~tlee
Major Research Areas
Research Summary
High-speed and low-power analog to digital converter/digital-to-analog converter
Phase-Locked Loop System
Broadband equalizer and clock and data recovery circuit
Tai-Cheng Lee (李泰成) was born in Taiwan, R.O.C, in 1970. He received the B.S. degree from National Taiwan University in 1992 , the M.S. degree from Stanford University in 1994 and the Ph.D. degree from the University of California, Los Angeles in 2001, all in electrical engineering.
He worked for LSI logic from 1994 to 1997 as a circuit design engineer. He served as an adjunct assistant professor at graduate institute of electronics engineering (GIEE), National Taiwan University from 2001 to 2002. Since 2002, he has been with electrical engineering department and GIEE, National Taiwan University, where he is a professor. His main research interests are in high-speed mixed-signal and analog circuit design, data converters, PLL systems and RF circuits.
Journal articles & book chapters
1. G-C Chen and T-C Lee, “An 8 Gb/s Far-End Crosstalk Cancelation and FFE Co-Designed TX Output Driver” , IEEE Solid-State Circuit Letters , Vol. 7 , 227-230, Jul. 2024
2. S-Y Wang and T-C Lee, “A An 800-MS/s 8.2-ENOB TDC-assisted Pipelined-SAR ADC With Parallel Conversion” , IEEE Transactions on Circuits and Systems, Part II , Apr. 2024
3. C-Y Hsu and T-C Lee, “A Calibration-Free 9.3-ENOB 1-GS/s Pipelined ADC With PVT-Insensitive Nested Ring Amplifiers” , IEEE Transactions on Circuits and Systems , 2024
4. H-H Chang, C-R Chen, and T-C Lee, “A 511-μW 89-dB-SNDR Asynchronous SAR-ISDM ADC With Noise Shaping Dynamic Amplifier and Time-Domain Noise-Slicing Technique” , IEEE Journal of Solid-State Circuits , Vol. 59 , 2199-2208, Jul. 2024
5. Y-H Yang, and T-C Lee, “A Sub-Baud-Rate Wireline Receiver With One-Tap DFE” , IEEE Journal of Solid-State Circuits , Nov. 2024
6. Y-C Chan, W-C Chen, and T-C Lee, “A 0.9-V 50-MS/s 67.3-dB-SNDR SAR-ISDM ADC With an Oscillator-Based Integrator,” , IEEE Transactions on Circuits and Systems, Part II , Sep. 2023
7. H-H Chang, T-C Lin, and T-C Lee, “A Single-Channel 1-GS/s 7.48-ENOB Parallel Conversion Pipelined SAR ADC With a Varactor-Based Residue Amplifier” , IEEE Transactions on Circuits and Systems, Part II , Vol. 63 , 813-817, Apr. 2022
8. Y-H Yang and T- Lee, “A Wireline Termination Embedded Energy Harvesting System With 300-W Extracted” , IEEE Solid-State Circuit Letters , Vol. 3 , 398-403, Nov. 2020
9. C-Y Lin, Y-H Wei, and T-C Lee, “A 10b 2.6GS/s Time-Interleaved SAR ADC with Background Timing-Skew Calibration” , IEEE Journal of Solid-State Circuits , Vol. vol.53 no.5 , 1508-1517, May 2018
10. W-S Chang and T-C Lee, “A 5 GHz Fractional- N ADC-Based Digital Phase-Locked Loops With −243.8 dB FOM” , IEEE Transactions on Circuits and Systems, Part I , Nov. 2016
11. C-Y Lin, C-H Wong, C-H Hsu, Y-H Wei, and T-C Lee, “A 200-MS/s Phase-Detector-Based Comparator with 400-uVrms Noise” , IEEE Transactions on Circuits and Systems, Part II, , Apr. 2016
12. C-Y Lin and T-C Lee, “A 12-bit 210-MS/s 2-Times Interleaved Pipelined-SAR ADC With a Passive Residue Transfer Technique” , IEEE Transactions on Circuits and Systems, Part I , Jul. 2016
13. S-C Wu and T-C Lee, “Ultra-Low Power One-Pin Crystal Oscillator with Self-Charged Technique” , IET Electronic Letters , Apr. 2016
14. C-L Chang and T-C Lee, “A Compact Multi-Input Power Conversion System with High Time-Efficiency Inductor–Sharing Technique for Thermoelectric Energy Harvesting Applications” , Journal of Circuits, Systems and Computers (JCSC) , Jan. 2016
15. P-C Huang, W-S Chang and T-C Lee, “A 2.3-GHz Fractional-N Divider-less Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise” , IEEE Journal of Solid-State Circuits , Vol. vol 49, no. 12 , pp. 2964-2975-, Dec. 2014
16. C-C Lee and T-C Lee, “A 2.4-GHz High Efficiency Adaptive Power Harvester” , IEEE Transactions on Very Large Scale Integration Systems , Vol. vol 22, no. 2 , pp. 434-438-, Feb. 2014
17. C-H Wong and T-C Lee, “A 6-GHz Self-Oscillating Spread-Spectrum Clock Generator” , IEEE Transactions on Circuits and Systems, Part I , Vol. vol. 58, no. 3 , pp. 1264-1273-, May 2013
18. C-D Su, C-W Lee and T-C Lee, “A 6-GHz All Digital PLL for Spread Spectrum Clock Generators (SSCG)” , International Journal of Electrical Engineering , Jun. 2012
19. Y-C Huang and T-C Lee, “A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques” , IEEE Transactions on Circuits and Systems, Part I , pp. 1157-1166-, Jun. 2011
20. Z-Z Chen and T-C Lee, “The Design and Analysis of Dual-Delay-Path Ring Oscillators” , IEEE Transactions on Circuits and Systems, Part I , pp. 470-478-, Mar. 2011
21. Z-Z Chen and T-C Lee, “The Study of a Dual-Mode Ring Oscillator” , IEEE Transactions on Circuits and Systems, Part II , pp. 210-214-, Jan. 2011
22. Yen-Chuan Huang and Tai-Cheng Lee, “A 0.02-mm2 9-bit 50-MS/s Cyclic ADC in a 90-nm Digital CMOS Technology” , IEEE Journal of Solid-State Circuits , Mar. 2010
23. T-C Lee and C-H Lin, “Nonlinear R-2R Transistor-Only DAC” , IEEE Transactions on Circuits and Systems, Part I , Nov. 2010
24. K-T Chen and T-C Lee, “A 320-MHz CMOS Continuous-Time ΔΣ Modulator With 5-MHz Signal Bandwidth and 8.3-bit ENOB” , International Journal of Electrical Engineering , Jun. 2010
25. Li-Han Hung; Tai-Cheng Lee, “A Split-Based Digital Background Calibration Technique in Pipelined ADCs” , IEEE Transactions on Circuits and Systems, Part II , Nov. 2009
26. K-J Hsian and Tai-Cheng Lee, “A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation” , IEEE Journal of Solid-State Circuits , Sep. 2009
27. Zuow-Zun Chen and Tai-Cheng Lee, “A Multiphase Compensation Method with Dynamic Element Matching Technique in S-D Fractional-N Frequency Synthesizers” , Journal of Semiconductor Technology and Science , Sep. 2008
28. K-J Hsiao and T-C Lee, “A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning” , IEEE Journal of Solid-State Circuits , Jun. 2008
29. D.-L. Shen and T.-C. Lee, “A 6-b 800-MS/s Pipelined A/D Converter with Open-Loop Amplifiers” , IEEE Journal of Solid-State Circuits , Feb. 2007
30. T.-C. Lee and Y.-C. Huang, “The design and analysis of a Miller Divider Based Clock Generator for MBOA-UWB Application” , IEEE Journal of Solid-State Circuits , Jun. 2006
31. T.-C. Lee and K.-J. Hsiao, “The design and analysis of a DLL-Based Frequency Synthesizer for UWB Application” , IEEE Journal of Solid-State Circuits , Jun. 2006
32. T.-C. Lee and C.-C. Chen, “A Mixed-Signal GFSK Demodulator for Bluetooth” , IEEE Transactions on Circuits and Systems Part II , Mar. 2006
33. T. C. Lee and B. Razavi, “A Stabilization Technique for Phase-Locked Frequency Synthesizers” , IEEE Journal of Solid-State Circuits , Jun. 2003
34. T. C. Lee and B. Razavi, “A 4-Tap 125-MHz Mixed-Signal Echo Canceller for Gigabit Ethernet on Copper Wire” , IEEE Journal of Solid-State Circuits , Mar. 2001
Conference & proceeding papers:
1. Y-P Lai, H-H Chang and T-C Lee, “An Asynchronous Zero-Crossing-Based Incremental Delta-Sigma Converter” , IEEE VLSI-DAT , Apr. 2022
2. C-T Chen, Y-H Yang and T-C Lee, “ Type-3 FMCW Radar Synthesizer with Wide Frequency Modulation Bandwidth” , IEEE ISCAS , May 2022
3. H-H Ding and T-C Lee, “ 5.25-GHz Sub-Sampling PLL with a VCO Phase Noise Suppression Technique” , International Solid-State Circuits Conference, San Francisco, Feb, 2020 , Feb. 2020
4. H-C Cheng and T-C Lee, “The Analysis and Design of a Self-Charged Crystal Oscillator with Pulse Regulating Feedback Loop” , IEEE VLSI-DAT , Apr. 2020
5. K-R Li, W-S Chang and T-C Lee, “A 5 GHz Outer-loop Phase Noise Filter With Delay-Sampling Technique” , IEEE ISCAS , May 2020
6. Y-H Yang and T- Lee, “ Wireline Termination Embedded Energy Harvesting System With 300-W Extracted” , IEEE A-SSCC , Nov. 2020
7. C-L Chiang, C-Y Lin and T-C Lee, “A 1.6-GS/s 8-bit Single Channel SAR ADC with Passive Residue Transfer” , International Conference on Analog VLSI Circuits 2019 , Oct. 2019
8. Y-L Hsieh and T-C Lee, “A SAR-Assisted Continuous-Time Incremental ΣΔ ADC With First-Order Noise Coupling” , IEEE ASICON , Nov. 2019
9. T-C Lee and D-N Jhou, “A 5-GHz Chirp Frequency Synthesizer with a Low 1/f Noise LC Oscillator” , PIERS 2018 , Toyama , Jul. 2018
10. D-N Jhou, W-S Chang, and T-C Lee, “A 5.12-GHz Fractional-N clock multiplier with an LC-VCO-based MDLL” , IEEE Symposium on VLSI Circuits , Jun. 2017
11. J-C Hsiao and T-C Lee, “A 10-Gb/s Equalizer with Digital Adaptation” , International SoC Design Conference , Nov. 2017
12. W-S Chang, D-N Jhou, Y-H Yang and T-C Lee, “An Energy-Efficient Self-Charged Crystal Oscillator with a Quadrature-Phase Shifter Technique” , IEEE Asian Solid-State Circuit Conference , Dec. 2017
13. C-Y Lin, Y-H Wei, and T-C Lee, “A 10b 2.6GS/s Time-Interleaved SAR ADC with Background Timing-Skew Calibration” , International Solid-State Circuits Conference , Feb. 2016
14. B-C Lin,W-S Chang and T-C Lee, “A 2X25Gb/s 20mW serializing transmitter with 2.5:1 multiplexers in 40nm technology” , IEEE VLSI-DAT , Apr. 2016
15. C-L Chang and T-C Lee, “An thermoelectric and RF multi-source energy harvesting system” , 2016 2nd International Conference on Intelligent Green Building and Smart Grid (IGBSG) , Jul. 2016
16. C-P Wang and T-C Lee, “ Technique for In-Band Phase Noise Reduction in Fractional-N Frequency Synthesizers” , IEEE Asian Solid-State Circuit Conference , Nov. 2016
17. C-K Hsu and T-C Lee, “A Single-Channel 10-b 400-MS/s 8.7-mW Pipeline ADC in a 90-nm Technology” , IEEE Asian Solid-State Circuit Conference , Nov. 2015
18. T-Y Wang and T-C Lee, “An 84.7-DR Wide BW Incremental ADC” , IEEE VLSI-DAT , Apr. 2015
19. P-C Huang, W-S Chang and T-C Lee, “A 2.3-GHz Fractional-N Divider-less Phase-Locked Loop with -112dBc/Hz In-Band Phase Noise” , International Solid-State Circuit Conference , San Francisco , Feb. 2014
20. C-L Chang and T-C Lee, “A Compact Multi-Input Thermoelectric Energy Harvesting System with 58.5% Power Conversion Efficiency and 32.4-mW Output Power Capability” , International Symposium on Integrated Circuits , Dec. 2014
21. L-H Chiueh and T-C Lee, “A 6-Gb/s Adaptive-Loop-Bandwidth Clock and Data Recovery (CDR) Circuits” , IEEE Asian Solid-State Circuit Conference , Nov. 2014
22. Y-H Kang, C-Y Lin and T-C Lee, “ A 20-MHz BW 75-dB SFDR shifted-averaging VCO-based ΔΣ modulator” , IEEE ISCAS , Jun. 2014
23. C-Y Lin and T-C Lee, “A 12-bit 210-MS/s 5.3-mW pipelined-SAR ADC with a passive residue transfer technique” , IEEE Symposium on VLSI Circuits , Jun. 2014
24. J-A Cheng, W-S Chang and T-C Lee, “A 3X-oversampling hybrid clock and data recovery circuit with programmable bandwidth” , IEEE VLSI-DAT , Apr. 2014
25. C-Y Lin and T-C Lee, “Jitter Error Cancellation Technique in Digital Domain for ADC” , IEEE VLSI-DAT , Apr. 2013
26. C-Y Lin Y-C Huang and T-C Lee, “Analysis of the Leakage Effect in a Pipelined ADC with Nanoscale CMOS Technologies” , IEEE VLSI-DAT , Apr. 2013
27. C-C Ho and T-C Lee, “A 10-bit 200-MS/s Reconfigurable Pipelined A/D Converter” , IEEE VLSI DAT , Apr. 2012
28. Y-C Huang, C-Y Lin and T-C Lee, “A 10-b 400Ms/s 36mW interleaved ADC” , IEEE RFIT Symposium , Dec. 2011
29. P Zhang, T-C Lee, “Spilt-based Digital Background Calibration of Multistage Nonlinear Errors in Pipelined ADCS” , International Conference on Sampling Theory and Applications , May 2011
30. K Fong, Z-Z Chen and T-C Le, “An All‐Digital De‐skew Clock Generator for Arbitrary Wide Range Delay” , IEEE Asian Pacific Conference on Circuits and Systems , Dec. 2010
31. Y-C Hung, K Fong and T-C Lee, “A 300- to 800-MHz De-Skew Clock Generator for Arbitrary Delay” , IEEE Asian Solid-State Circuit Conference , Nov. 2010
32. C-Y Lin, C-Y Chiang and T-C Lee, “An Offset Phase-Locked Loop Spread Spectrum Clock Generator for SATA III” , IEEE Custom Integrated Circuits Conference , Sep. 2010
33. Yen-Chuang Huang and Tai-Cheng Lee, “A 10-bit 100 MS/s 4.5 mW Pipelined ADC with a Time Sharing Techniques” , International Solid-State Circuit Conference , San Francisco , Feb. 2010
34. Feng-Chiu Hsieh and Tai-Cheng, “A 6-bit Pipelined Analog-to-Digital Converter with Current-Switching Open-Loop Residue Amplification” , IEEE Asian Solid-State Circuit Conference , Fukuoka, Japan , Nov. 2008
35. Shih-Chun Lin and Tai-Cheng Lee, “An 833-MHz 132-Phase Multiphase Clock Generator with Self-Calibration Circuits” , IEEE Aisan Solid-State Circuit Conference , Fukuoka, Japan , Nov. 2008
36. K-J Hsiao, M-H Lee and T-C Lee, “ A CLOCK AND DATA RECOVERY CIRCUIT WITHWIDE LINEAR RANGE FREQUENCY” , IEEE VLSI-DAT , Apr. 2008
37. Y-C Huang, Q-T Chen and T-C Lee, “A 4-PAM Adaptive Analog Equalizer for Backplane Interconnections” , IEEE VLSI-DAT , Apr. 2008
38. K-J Hsiao and T.-C. Lee, “A Low-Jitter 8GHz to 10GHz Distributed DLL for Multiple-Phase Clock Generation” , IEEE International Solid-State Circuit Conference , Feb. 2008
39. D.-L Shen, Y-C Lai and T.-C. Lee, “A 10-Bit Binary-Weighted DAC with Digital Background LMS Calibration” , IEEE Asian Solid-State Circuit Conference , Nov. 2007
40. K-J Hsiao and T-C Lee, “A Fully Integrated 36MHz to 230MHz Multiplying DLL with Adaptive Current Tuning” , Symposium on VLSI Circuits , Jun. 2007
41. G-J Chen, H-H Chiu and T-C Lee, “A 4-Channel Poly-Phase Filter for Cognitive Radio Systems” , IEEE VLSI-DAT , Apr. 2007
42. H-S Kao, M-J Yang, T-C Lee, “A Delay-Line-Based GFSK Demodulator for Low-IF Receivers” , International Solid-State Circuit Conference (ISSCC) , Feb. 2007
43. Q.-T. Chen, Y.-C. Huang and T.-C. Lee, “A 14Gb/s 4PAM Adaptive Analog Equalizer for 40-inch Backplane Interconnections” , Asian Solid-State Circuit Conference (ASSCC) , Nov. 2006
44. D-L Shen and T-C Lee, “A 6-b 800-MS/s Pipelined A/D Converter with Open-loop Amplifiers” , IEEE Symposium on VLSI Circuits , Jun. 2006
45. Y-M Liao and T-C Lee, “A 6-b 1.3Gs/s A/D Converter with C-2C Switch–Capacitor Technique” , IEEE VLSI-DAT , Apr. 2006
46. T.-C. Lee and W.-L. Lee, “ A Spur-Suppression Technique for Phase-Locked Frequency Synthesizers” , IEEE International Solid-State Circuit Conference (ISSCC) , Feb. 2006
47. T.-C. Lee and etal, “A 40-GHz Distributed-Load Static Divider” , IEEE Asian Solid-State Circuit Conference , Nov. 2005
48. T. C. Lee and K-J Hsiao, “A DLL-Based Frequency Multiplier For MBOA-UWB System” , IEEE Symposium on VLSI Circuits , Jun. 2005
49. T. C. Lee and Y. C. Huang, “A Miller Divider Based Clock Generator for MBOA-UWB Application” , IEEE Symposium on VLSI Circuits , Jun. 2005
50. D. L. Shen and T. C. Lee, “A Linear-Approximation Technique for Digitally-Calibrated Pipelined ADCs” , ISCAS , May 2005
51. T. C. Lee and Y. C. Huang, “An Optimization Technique for RF Buffers with Active Inductors” , ISCAS , May 2005
52. Y. H. Chen, and T. C. Lee, “ 6 bits 500-Ms/s Digital Self-Calibrated Pipelined Analog-to-Digital Converter” , AP-ASIC , Aug. 2004
53. H. C. Wang, H. S. Kao, and T. C. Lee, “An 8-bit 2-V 2-mW 0.25-mm2 CMOS DAC” , AP-ASIC , Aug. 2004
54. T. C. Lee and B. Razavi, “A Stabilization Technique for Phase-Locked Frequency Synthesizers” , IEEE VLSI Circuits Symposium , Kyoto, Japan , Jun. 2001
55. T. C. Lee and B. Razavi, “A 125-MHz Mixed-Signal Equalizer for Gigabit Ethernet on Copper Wire” , IEEE Custom Integrated Circuits Conference , San Diego , May 2001
56. T. C. Lee and B. Razavi, “A 4-Tap 125-MHz Mixed-Signal Echo Canceller for Gigabit Ethernet on Copper Wire” , IEEE Custom Integrated Circuits Conference , Orlando , May 2000
57. 5. Y-H Wei, C-Y Lin, and T-C Lee, “A 12-bit 600-MS/s time-interleaved SAR ADC with background timing skew calibration” , IEEE International Symposium on Radio-Frequency Integration Technology (RFIT) , 0000
Books:
1. T. C. Lee, “High-Speed CMOS Circuits for Gigabit Ethernet” , Ph.D. dissertation , UCLA, Jan. 2001
Patents:
1. T-C Lee, C-Y Lin and Y-H Wei, “Analog-to-digital converting system and converting method” , US 9,685,970, Jul. 2016
2. T-C Lee and C-W Wong, “Circuit for spread spectrum transmission and method thereof” , US 8,787,424, Jul. 2014
3. Y-C Huang and T-C Lee, “Pipelined analog-to-digital converter and method for converting analog signal to digital signal,” , US 8,471,753, Jun. 2013
4. T-C Lee and C-H Lin, “Digital-to-analog converter (DAC) and an associated method” , US Patent 7982650, Jun. 2011
5. L-H Hung and T-C Lee, “Method for achieving high-speed analog-to-digital conversion without degrading accuracy, and associated apparatus” , US 7932849, Apr. 2011
6. T-C Lee and B. Razavi, “A Stabilization technique for phase-locked frequency synthesizers” , US 6864753, Mar. 2005