陳信樹 Chen, Hsin-Shu
- 國立台灣大學電機工程學系 專任教授
- 臺大輻射應用與抗輻射技術研究中心 中心主任
- Ph.D. Univ. of Illinois, Urbana
- M.S. University of California, Los Angeles
- B.S. National Taiwan University
- 辦公室 : 電機二館 246
- 電話 : +886-2-33665879
- 傳真 : +886-2-2368-1679
- Email :
- Office Hour : Mon. 13:00-15:00
- 個人網頁 : http://cc.ee.ntu.edu.tw/~hschen/
- 相關連結1 : https://rtrc.ntu.edu.tw/
主要研究領域
研究領域摘要
本實驗室的研究領域包括了低功率、高速、高解析度的“類比/數位轉換器”與“數位/類比轉換器”應用於有線/無線通訊，類比前端電路應用於物聯網感測裝置、60GHz收發機及寬頻高速的高階量測儀器系統，電源能量擷取系統，低抖動鎖相迴路/延遲鎖定迴路時脈產生應用於混合信號系統和類比/混合信號積體電路設計實作應用於系統晶片。類比/數位轉換器的架構包括了循序漸近式(SAR)、管線(pipeline)、子區間(subranging)、快閃(flash) 和時間交錯(time-interleave)。數位/類比轉換器的研究將專注於電流切換區段(current-steering segmented)架構。就能量擷取電源轉換器的研究而言，要達成高效率和低暫態突波。就低抖動鎖相迴路/延遲迴路的研究而言，將強調其使用來避免時脈誤差(clock skew)在高速高精確度的類比/數位轉換器系統。就高速I/O電路的研究而言，結合信號與電源完整度的考量，將達成高速、低電源電壓的目標。總的來說，研究專注於低功率、高速混合信號積體電路設計。
Our Lab's research areas would include low-power, high-speed, high-precision Analog-to-Digital Converters (ADCs) and Digital-to-Analog Converters (DACs) for wire/wireless communications, analog-frond-end (AFE) circuit for IoT sensor, 60GHz/77GHz/84GHz transceiver and wideband high-speed high-end measurement equipment system, Energy-Harvesting Power IC Design, low-jitter Phase-Locked Loop (PLL)/Delay-Locked Loop (DLL) clock generation in mixed-signal systems, and practical aspects of analog/mixed-signal Integrated Circuit (IC) design for System-On-Chip (SOC). The A/D Converter architectures will include SAR, pipeline, subranging, flash, and time-interleave. The D/A Converters will focus on the current-steering segmented architecture. The AC-DC and DC-DC Converters would achieve high efficiency and low transient ripple. The research interest on the low-jitter PLL/DLL would emphasize on its usage to avoid the clock skew in a high-speed, high-precision sampled-data system such as an ADC system. The design of high-speed I/O circuit would combine with signal and power integrity considerations to produce high-speed, low-voltage interface circuitry. In general, the research focuses on low-power high-speed mixed-signal IC design.
Hsin-Shu Chen (陳信樹) received B.S. degree in electrical engineering from National Taiwan University, Taiwan in 1989, and M.S. degree from University of California at Los Angeles in 1992. He received his Ph.D. degree from University of Illinois at Urbana-Champaign in 2001. He was a full-time teaching assistant with the Department of Electrical Engineering at National Taiwan University from 1989 to 1990. From 1992 to 1993 he was with LinCom Corporation in Los Angeles, California, where he was involved in satellite communication system design and firmware design for spread spectrum cordless phone. From 1994 to 1996 he was a graduate research assistant in the Coordinated Science Laboratory of the Department of Electrical and Computer Engineering in the University of Illinois at Urbana-Champaign, concentrating on the design of analog-to-digital converters. From 1996 to 2002 he was with Intersil Corporation in Melbourne, Florida, as a data converter design engineer. From 2002 to 2003 he was with Maxim Integrated Products Inc. Melbourne Design Center as a mixed-signal circuit designer. Since 2003, he has been with the Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan and now he is a professor. His current research interests include energy-efficient data conversion technique, low-jitter clock generation, and energy-harvesting power converter design. Dr. Hsin-Shu Chen is a member of IEEE and served as an Associate Editor of IEEE Transactions on Circuits and Systems-II: Express Briefs from 2007 to 2009. He currently serves as an Editorial Board Member of Journal AICSP and a TPC member of RFIT.
Journal articles & book chapters
1. Yu,Liang,Hung,Chen,Liao,Li,Chen,Chen,Tseng, “Pulsed-Laser-Induced Single-Event Upset in Dynamic Comparator by Incorporating Experimental Parameters Into Simulations” , IEEE Transactions on Instrumentation and Measurement , Vol. 73 , 1-12, 2024
2. Chi-Wei Chen, Weining Zeng Pranoto, Hsin-Shu Chen, and Wen-Jong Wu, “A 0.25-μm HV-CMOS Synchronous Inversion and Charge Extraction Interface Circuit With a Single Inductor for Piezoelectric Energy Harvesting” , IEEE Transactions on Power Electronics , Vol. 38 , 15707-15718, Dec. 2023
3. Hsin-Shu Chen, Chien-Jian Tseng, Cheng-Ming Chen, and Hsiang-Wen Chen, “A 34.3 dB SNDR, 2.3GS/s, Sub-Radix Pipeline ADC using Incomplete Settling Technique with background radix detector” , Analog Integrated Circuits and Signal Processing , Vol. 107 , 39-50, Mar. 2021
4. Hsin-Shu Chen, Chien-Jian Tseng, Yu-Wei Chuan, and Chun-Wei Chang, “A 10-bit 300 MS/s Pipeline ADC with Time-Domain MDAC” , Analog Integrated Circuits and Signal Processing , Vol. 108(2) , 241-255, May 2021
5. Yao-Sheng Hu, Li-Yu Huang, and Hsin-Shu Chen, “A 0.6 V 1.63 fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System” , IEEE Journal of Solid-State Circuits , Vol. Vol. 54, No. 10 , pp. 2680-2690, Oct. 2019
6. Pang-Jung Liu, Rui-Min Lin, and Hsin-Shu Chen, “Two-Input Floating Buck Converter with Variable Off-Time Control Scheme for High-Efficiency and -Accuracy LED Lighting,” , IEEE Journal of Emerging and Selected Topics in Power Electronics , Vol. Vol. 6, No. 2 , pp. 563-570, Jun. 2018
7. Pang-Jung Liu, Yu-Min Lai, Ping-Chieh Lee, and Hsin-Shu Chen, “A Fast-Transient DC-DC Converter with Hysteresis Prediction Voltage Control” , IET Transactions on Power Electronics , Vol. Vol. 10, No. 3 , pp. 271-278, Mar. 2017
8. Yao-Sheng Hu, Po-Chao Huang, Hung-Yen Tai, and Hsin-Shu Chen, “A 12.5fJ/conversion-step 8-bit 800 MS/s Two-Step SAR ADC” , IEEE Trans. on Circuits and Systems-II: Express Briefs Paper , Vol. Vol. 63, No. 12 , pp.1166-1170, Dec. 2016
9. Tsung-Han Tsai, Hung-Yen Tai, Pao-Yang Tsai, Cheng-Hsueh Tsai, and Hsin-Shu Chen, “An 8b 700MS/s 1b/cycle SAR ADC Using a Delay-Shift Technique” , IEEE Trans. on Circuits and Systems-I: Regular Papers , Vol. Vol. 63, No. 5 , pp. 683-692-, May 2016
10. Chien-Jian Tseng, Chieh-Fan Lai, and Hsin-Shu Chen, “A 6-Bit 1 GS/s Pipeline ADC Using Incomplete Settling With Background Sampling-Point Calibration” , IEEE Trans. on Circuits and Systems-I: Regular Papers , Vol. Vol. 61, No. 10 , pp. 2805-2815, Oct. 2014
11. Hung-Yen Tai, Cheng-Hsueh Tsai, Pao-Yang Tsai, Hung-Wei Chen, and Hsin-Shu Chen, “A 6-bit 1 GS/s Two-Step SAR ADC in 40 nm CMOS” , IEEE Trans. on Circuits and Systems-II: Express Briefs Paper , Vol. Vol. 61, No. 5 , pp. 339-343-, May 2014
12. Chien-Jian Tseng, Yi-Chun Hsieh, Ching-Hua Yang, and Hsin-Shu Chen, “A 10-bit 200MS/s Capacitor-Sharing Pipeline ADC” , IEEE Trans. on Circuits and Systems-I: Regular Papers , Vol. Vol. 60, No. 11 , pp. 2902-2910-, Nov. 2013
13. Pang-Jung Liu, Jia-Nan Tai, Hsin-Shu Chen, Jau-Horng Chen, and Yi-Jan Emery Chen, “Spur-Reduction Design of Frequency-Hopping DC-DC Converters” , IEEE Transactions on Power Electronics , Vol. Vol. 27, No. 11 , pp. 4763-4771-, Nov. 2012
14. Chien-Jian Tseng, Hung-Wei Chen, Wei-Ting Shen, Wei-Chih Cheng, and Hsin-Shu Chen, “A 10-bit 320MS/s Stage-Gain-Error Self-Calibration Pipeline ADC” , IEEE Journal of Solid-State Circuits , Vol. Vol. 47, No. 6 , pp. 1334-1343-, Jun. 2012
15. Pang-Jung Liu, Wei-Shan Ye, Jia-Nan Tai, Hsin-Shu Chen, Jau-Horng Chen, and Yi-Jan Emery Chen, “A High-Efficiency CMOS DC-DC Converter with 9-µs Transient Recovery Time” , IEEE Trans. Circuits and Systems-I: Regular Papers , Vol. Vol. 59, No. 3 , pp. 575-583-, Mar. 2012
16. Pang-Jung Liu, Wei-Shan Ye, Jia-Nan Tai, Hsin-Shu Chen, Jau-Horng Chen, and Yi-Jan Emery Chen, “A High-Efficiency CMOS DC-DC Converter with 9-μs Transient Recovery Time” , IEEE Trans. on Circuits and Systems-I: Regular Papers , Vol. Vol. 59, No. 3 , pp. 575-583-, Mar. 2012
17. Hsin-Shu Chen, and Jyun-Cheng Lin, “A Fast-Lock Low-Power Subranging Digital Delay-Locked Loop” , IEICE Transactions on Electronics , Vol. Vol. E93-C, No. 6 , Jun. 2010
18. Hao-Hsiang Chuang, Wei-Da Guo, Yu-Hsiang Lin, Hsin-Shu Chen, Yi-Chang Lu, Jacky Hong, Chun-Huang Yu, Argy Cheng, Jonathan Chou, Chuan-Jen Chang, Joseph Ku, Tzong-Lin Wu, and Ruey-Beei Wu, “Signal/Power Integrity Modeling of High-Speed Memory Modules Using Chip-Package-Board Co-Analysis” , IEEE Transactions on Electromagnetic Compatibility , Apr. 2010
19. Hung-Wei Chen, I-Ching Chen, Huan-Chieh Tseng, and Hsin-Shu Chen, “A 1-GS/s 6-bit Two-Channel Two-Step ADC in 0.13-um CMOS” , IEEE Journal of Solid-State Circuits , Vol. Vol. 44, No. 11 , pp. 3051-3059-, Nov. 2009
20. Li-Yuan Yang, Hsin-Shu Chen, and Yi-Jan Emery Chen, “A 2.4 GHz Fully Integrated Cascode-Cascade CMOS Doherty Power Amplifier” , IEEE Microwave and Wireless Components Letters , Vol. Vol. 18, No. 3 , pp. 197-199-, Mar. 2008
21. Hsin-Shu Chen, Bang-Sup Song and Kantilal Bacrania, “A 14b 20MSamples/s CMOS Pipelined ADC” , IEEE Journal of Solid-State Circuits , Vol. Vol. 36, No. 6 , pp. 997-1001-, Jun. 2001
Conference & proceeding papers:
1. Sharon Isabelle Timotius, Yi-Lun Wang, and Hsin-Shu Chen, “An SRAM-Based PUF with High Native-Stability Using Alternative Configuration Technique” , IEEE ICCE 2025 , Las Vegas, NV , Jan. 2025
2. Jun-Yi Wu and Hsin-Shu Chen, “A Highly Multi-Bit Continuous-Time Delta-Sigma Modulator ADC with 9-Bit Feedback” , 2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS) , Tempe, AZ, USA , Aug. 2023
3. Chi-Wei Chen, Su-Chien Yu and Hsin-Shu Chen, “A PVT-Invariant Front-End Ring Amplifier using Self-Stabilization Technique for SAR ADC” , IEEE ISCAS , Austin, TX , May 2022
4. Chi-Wei Chen, Bao-Xian Peng, and Hsin-Shu Chen, “A 96.6%-Peak-Efficiency and Seamless-Mode-Transition Buck-Boost DC-DC Converter with Auto-Shift-Ramp (ASR)” , IEEE Asian Solid-State Circuits Conf. , Taipei, Taiwan , Nov. 2022
5. Pei-Kai Liao, Yu-Lin Chen, Hsin-Shu Chen, Jia-Han Li1, Pei-Yuan Chu, Chia-Ray Chen, and Chien-Kai Tseng,, “Single Event Effect of the Combinational Circuit by Femtosecond Pulse Laser” , JSAP-OSA Joint Symposia 2021 , Nagoya, Japan , Sep. 2021
6. Pei-Kai Liao, Yu-Lin Chen, Hsin-Shu Chen, Jia-Han Li, Pei-Yuan Chu, Chia-Ray Chen, and Chien-Kai Tseng, “Short Pulse Laser and Proton Beam for Testing Single Event Effect on Digital Inverter Circuit” , 2021 AASRC Conference , 雲林, 台灣 , Oct. 2021
7. Tun-Yen Liao, Hsin-Shu Chen , and Wen-Jong Wu, “Reconfigurable Switched-Capacitor DC-DC Converter with Adaptive Switch Modulation and Frequency Scaling Techniques” , IEEE ISCAS , Daegu, Korea , May 2021
8. Hsin-Shu Chen, Sheng-Hsiang Huang, Hung-Yen Tai, Sen-Wei Lin, and Shi-Wei Wu, “A 6b 1GS/s 2b/Cycle SAR ADC with Body-Voltage Offset Calibration” , IEEE ISCAS , Seville, Spain , Oct. 2020
9. Hsin-Shu Chen, Chien-Jian Tseng, Cheng-Ming Chen, Hsiang-Wen Chen and Hamed Alsuraisry, “A 34.3dB SNDR, 2.3GS/s, Sub-Radix Pipeline ADC Using Incomplete Settling Technique With Background Radix Detector,” , Institute of Electrical Engineers of Japan (IEEJ) International Conference on Analog VLSI Circuits , Yilan, Taiwan , Oct. 2019
10. Hsin-Shu Chen, Chien-Jian Tseng, Yu-Wei Chuan, Chun-Wei Chang, Abdulelah Alshehri, Mazen Almalki and Abdulhamid Sayed, “A 10-bit 300 MS/s Pipeline ADC With Time Domain MDAC,” , Institute of Electrical Engineers of Japan (IEEJ) International Conference on Analog VLSI Circuits , Yilan, Taiwan , Oct. 2019
11. Chi-Wei Chen, Hsin-Shu Chen and Wen-Jong Wu, “A Fast-Transient Switched-Capacitor DC-DC Converter with a Current Sensing Control Technique” , IEEE MWSCAS , Dallas, TX, USA , Aug. 2019
12. Kai-Ren Cheng, Hsin-Shu Chen, Mickaël Lallart, and Wen-Jong Wu, “A 0.25μm HV-CMOS Synchronous Inversion and Charge Extraction (SICE) Interface Circuit for Piezoelectric Energy Harvesting” , IEEE ISCAS , Florence, Italy , May 2018
13. Yao-Sheng Hu, Li-Yu Huang, and Hsin-Shu Chen, “A 0.6V 1.63fJ/c.-s. Detective Open-Loop Dynamic System Buffer for SAR ADC in Zero-Capacitor TDDI System” , IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers , Tainan, Taiwan , Nov. 2018
14. Yao-Sheng Hu, Jhao-Huei Lin, Ding-Guo Lin, Kai-Yue Lin, and Hsin-Shu Chen, “An 89.55dB-SFDR 179.6dB-FoMS 12-bit 1MS/s SAR-Assisted SAR ADC with Weight-Split Compensation Calibration” , IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers , Tainan, Taiwan , Nov. 2018
15. Hsin-Shu Chen, Jia-Nan Tai, Jau-Horng Chen, and Yi-Jan Emery Chen, “A Current Average Control Method for Transient-Glitch Reduction in Variable Frequency DC-DC Converters” , IEEE ISCAS , Baltimore, MD, USA , May 2017
16. Yao-Sheng Hu, Kai-Yue Lin and Hsin-Shu Chen, “A 510nW 12-bit 200kS/s SAR-Assisted SAR ADC Using a Re-Switching Technique” , IEEE Dig. Symp. VLSI Circuits , Kyoto, Japan , Jun. 2017
17. Yao-Sheng Hu, Kai-Yue Lin, and Hsin-Shu Chen, “A 12-bit 200kS/s Subranging SAR ADC with an Energy-Curve Reshape Technique” , IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers , Toyama, Japan , Nov. 2016
18. Yao-Sheng Hu, Po-Chao Huang, Mi-Di Yang, Shi-Wei Wu, and Hsin-Shu Chen, “A 0.9V 15fJ/conversion-step 8-bit 1.5GS/s Two-Step SAR ADC” , IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers , Toyama, Japan , Nov. 2016
19. Po-Chao Huang, Yao-Sheng Hu, Hung-Yen Tai, and Hsin-Shu Chen, “An 8-bit 900MS/s Two-Step SAR ADC” , IEEE ISCAS , Montreal, Canada , May 2016
20. Yu-Chieh Hsieh, Jiun-Jung Chen, Hsin-Shu Chen, and Wen-Jong Wu, “An Integrated Circuit Design of High Efficiency Parallel-SSHI Rectifier for Piezoelectric Energy Harvesting” , PowerMEMS , Paris, France , Dec. 2016
21. Yao-Sheng Hu, Chi-Huai Shih, Hung-Yen Tai, Hung-Wei Chen and Hsin-Shu Chen, “A 0.6V 6.4fJ/conversion-step 10-bit 150MS/s Subranging SAR ADC in 40nm CMOS” , IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers , Kaohsiung, Taiwan , Nov. 2014
22. Hung-Yen Tai, Yao-Sheng Hu, Hung-Wei Chen, and Hsin-Shu Chen, “A 0.85fJ/conversion-step 10-bit 200kS/s subranging SAR ADC in 40nm CMOS” , IEEE International Solid-State Circuits Conf. Dig. Tech. Papers , San Francisco, CA, USA , Feb. 2014
23. Hung-Yen Tai, Pao-Yang Tsai, Cheng-Hsueh Tsai, and Hsin-Shu Chen, “A 0.004mm2 Single-Channel 6-bit 1.25GS/s SAR ADC in 40nm CMOS” , IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers , Singapore , Nov. 2013
24. Hung-Yen Tai, Hung-Wei Chen and Hsin-Shu Chen, “A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS” , IEEE Dig. Symp. VLSI Circuits , Honolulu, Hawaii, USA , Jun. 2012
25. Jia-Nan Tai, Hsin-Shu Chen and Hang-Quei Chiu, “A Highly Integrated Class-D Amplifier using Driver Delay Hysteresis Control” , IEEE VLSI-DAT , Hsinchu, Taiwan , Apr. 2012
26. Hung-Wei Chen, Wei-Ting Shen, Wei-Chih Cheng, and Hsin-Shu Chen, “A 10b 320MS/s Self-Calibrated Pipeline ADC” , IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers , Beijing, China , Nov. 2010
27. Hung-Wei Chen, Yu-Hsun Liu, Yu-Hsiang Lin, and Hsin-Shu Chen, “A 3mW 12b 10MS/s Sub-Range SAR ADC” , IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers , Taipei, Taiwan , Nov. 2009
28. Yu-Hsiang Lin, Jonathan Chou, Yi-Chang Lu, Tzong-Lin Wu, and Hsin-Shu Chen, “Chip-Package-Board Co-design – a DDR3 System Design Example from Circuit Designers’ Perspective” , IEEE EDAPS , Seoul, Korea , Dec. 2008
29. Hsin-Shu Chen and Chao-Ching Hung, “A Self-Calibrated Multiphase DLL-Based Clock Generator” , IEEE VLSI-DAT , Hsinchu, Taiwan , Apr. 2007
30. Chien-Kai Hung, Jian-Feng Shiu, I-Ching Chen and Hsin-Shu Chen, “A 6-bit 1.6 GS/s Flash ADC in 0.18-μm CMOS with Reversed-Reference Dummy” , IEEE Asian Solid-State Circuits Conf. Dig. Tech. Papers , Hangzhou, China , Nov. 2006
31. Sen-Wen Hsiao, Yen-Chih Huang, David Liang, Hung-Wei Kevin Chen and Hsin-Shu Chen, “A 1.5-V 10-ppm/ºC 2nd-Order Curvature-Compensated CMOS Bandgap Reference with Trimming” , IEEE ISCAS , Kos, Greece , May 2006
32. Tang-Nian Luo, Shuen-Yin Bai, Yi-Jan Emery Chen, Hsin-Shu Chen and Deukhyoun Heo, “A 1-V CMOS VCO For 60-GHz Applications” , Asia-Pacific Microwave Conference , Suzhou, China , Dec. 2005
33. Hsin-Shu Chen, Bang-Sup Song and Kantilal Bacrania, “A 14b 20MSamples/s CMOS Pipelined ADC” , IEEE International Solid-State Circuits Conf. Dig. Tech. Papers , San Francisco, CA, USA , Feb. 2000
34. Hsin-Shu Chen and Akira Ito, “Characterization of 1/f noise vs. number of gate stripes in MOS transistors” , IEEE ISCAS , Orlando, FL, USA , May 1999
Patents:
1. 曾千鑑和陳信樹, “管線式類比數位轉換方法及其裝置” , 台灣 發明第I548223號, Sep. 2016
2. 戴宏彥和陳信樹, “類比數位轉換電路及其轉換方法” , 台灣發明第I542158號, Jul. 2016
3. 戴宏彥、胡耀升和陳信樹, “類比數位轉換裝置及其轉換方法” , 台灣發明第I532328號, May 2016
4. 戴宏彥、陳宏維和陳信樹, “連續近似式類比至數位轉換器” , 台灣發明第I492547號, Jul. 2015
5. 劉邦榮和陳信樹, “電源轉換器舆控制方法” , 台灣發明第I499188號, Sep. 2015
6. Hung-Yen Tai, Yao-Sheng Hu, and Hsin-Shu Chen, “Analog to Digital Conversion Device and Analog to Digital Conversion Method” , U.S. Patent No: US9,143,153 B1, Sep. 2015
7. 陳信樹, “校正增益誤差的自校正系統及其自校正方法” , 台灣發明第I445318號, Jul. 2014
8. Hung-Yen Tai, Hung-Wei Chen, and Hsin-Shu Chen, “Successive Approximation Analog-To-Digital Converter,” , U.S. Patent No.: US8,742,971 B1, Jun. 2014
9. 陳宏維和陳信樹, “具自時脈的類比數位轉換裝置及其方法” , 台灣發明第I426711號, Feb. 2014
10. 陳宏維和陳信樹, “次區間的類比數位轉換裝置及其方法” , 台灣發明第I407702號, Sep. 2013
11. 洪健凱和陳信樹, “放大器陣列電路及快閃式類比數位轉換器” , 台灣發明第I335140號, Dec. 2010
12. Chien-Kai Hung, and Hsin-Shu Chen, “Amplifier Array Circuits and Flash Analog to Digital Converters” , U.S. Patent No.: US 7,554,477 B2, Jun. 2009
13. Hsin-Shu Chen, et al., “System and Method of DC Calibration of Amplifiers” , U.S. Patent No.: US 6,714,886 B2, Mar. 2004
14. Hsin-Shu Chen, et al., “Track and Hold with Dual Pump Circuit” , U.S. Patent No.: US6,731,155 B2, May 2004
15. Hsin-Shu Chen, et al., “An Analog to Digital Converter Using Subranging and Interpolation” , U.S. Patent No.: US6,570,523 B1, May 2003
16. Hsin-Shu Chen, et al., “Calibration of Resistor Ladder Using Difference Measurement and Parallel Resistive Correction” , U.S. Patent No.: US6,628,216 B2, Sep. 2003
Other publication:
1. 陳信樹, “高效能電路系統” , 工程科技通訊143期，pp25-26, Dec. 2014
2. 戴嘉南和陳信樹, “使用展頻技巧的脈衝寬度調變直流電壓轉換器” , 零組件雜誌，卷期230，pp104-105, Dec. 2010
3. 陳信樹, “子計畫五：運用於60GHz寬頻無線通訊系統之高速類比數位轉換器(3/3)” , 工程科技通訊107期，pp188-192, Aug. 2010
4. 陳信樹, “數位延遲鎖相迴路介紹” , 零組件雜誌，卷期186，pp74-78, Apr. 2007
5. 鍾政峰和陳信樹, “高速數位類比轉換器操作原理及設計考量” , 新電子雜誌, Jan. 2005
6. 杜明哲和陳信樹, “混合訊號電路元件—取樣電路的設計原理與挑戰” , 新電子雜誌, Feb. 2004