Professors

黃鐘揚 Huang, Chung-Yang

  • 國立台灣大學電機工程學系 專任教授
  • 國立台灣大學電子工程學研究所副教授
  • Ph.D. University of California at Santa Barbara, 2000
  • B.S. National Taiwan University, 1992
  • 辦公室 : 電機二館 444
  • 電話 : +886-2-33663644
  • 傳真 : +886-2-23671909
  • Email :
  • Office Hour : By e-mail appointment.
  • 個人網頁 : http://cc.ee.ntu.edu.tw/~ric/
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著作列表's top

主要研究領域

(1) SoC電路設計驗證, (2) 電路設計自動化及最佳化, (3) 可驗證性電路設計, (4) Constraint Satisfication問題

(1) design verification for SoCs, (2) design for verifiability, (3) design automation and optimization, and (4) constraint satisfaction problems in electronic design automation (EDA) area.

研究領域摘要

可靠性系統實驗室(三) 設計驗證工作室

本實驗室主要之研究領域為晶片系統(SoC)之設計驗證，其中的項目包括：

  1. 核心驗證引擎之研究與開發
  2. 網路、通訊、多媒體智財(IP)之驗證技術
  3. 系統設計分析與除錯技術
  4. Constraint Satisfaction Problem (CSP) 之各項應用。

綜合以上之研究，本實驗室正著手開發兩套驗證工具系統：

  1. Property Verification Framework
  2. IP Qualification Framework

Lab of Dependable Systems (3) Design Verification Team

The research focus of our lab is in the SoC (System on a Chip) design verification area, which includes:

  1. Sequential verification engines (e.g. ATPG, SAT, BDD, Arithmetic solver, etc)
  2. Network, communication, and multimedia IP verification techniques
  3. Design for Verifiability (DfV)
  4. System design analysis and debugging techniques
  5. Various applications of Constraint Satisfaction Problem (CSP)

We are implementing the above research topics into our own tools:

  1. Property Verification Framework
  2. IP Qualification Framework

    Professor Chung-Yang (Ric) Huang received his B.S. degree from Department of Electrical Engineering, National Taiwan University (NTUEE), in 1992. He obtained his PhD from Department of Electrical and Computer Engineering, University of California at Santa Barbara, in 2000. Before joining NTUEE as an assistant professor in 2004, he was with Cadence Design Systems, where he served as a senior R&D manager and was in charge of the core engine development of their functional verification tools. 

     

     

     

     

     

Journal articles & book chapters Conference & proceeding papers Books Patents
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Journal articles & book chapters

1. Jie-Hong R. Jiang, Chih-Chun Lee, Alan Mishchenko, and Chung-Yang (Ric) Huang, “To SAT or Not to SAT: Scalable Exploration of Functional Dependency” , IEEE Transactions on Computers (TCOMP) , Vol. vol. 59, no. 4 , pages 457-467-, Apr. 2010

2. R.C.-Y. Huang and K.-T. Cheng, “Using Word-Level ATPG and Modular Arithmetic Constraint-Solving Techniques for Assertion Property Checking” , IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems , Vol. , Volume 20, No. 3 , pp. 381-391-, Mar. 2001

3. S.-Y. Huang, K.-T. Cheng, K.-C. Chen, C.-Y. Huang, and F. Brewer, “AQUILA: An Equivalence Checking System for Large Sequential Designs” , IEEE Trans. on Computer , Vol. Vol. 49, No. 5 , pp. 443-464-, May 2000

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Conference & proceeding papers:

1. Yu-Fu Yeh, Chung-Yang (Ric) Huang, Chi-An Wu and Hsin-Cheng Lin, “Speeding Up MPSoC Virtual Platform Simulation by Ultra Synchronization Checking Method” , Proc. ACM/IEEE Design, Automation, and Test in Europe (DATE) conference , Mar. 2011

2. Shao-Lun Huang, Chi-An Wu, Kai-Fu Tang, Chang-Hong Hsu and Chung-Yang (Ric) Huang, “A Robust ECO Engine by Resource-Constraint-Aware Technology Mapping and Incremental Routing Optimization” , Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) , Jan. 2011

3. Chung-Yang (Ric) Huang, Yu-Fan Yin, Chih-Jen Hsu, Thomas B. Huang and Ting-Mao Chang, “SoC HW/SW Verification and Validation” , Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) , Jan. 2011

4. Bo-Han Wu, Chun-Ju Yang, Chung-Yang (Ric) Huang and Jie-Hong (Roland) Jiang, “A Robust Functional ECO Engine by SAT Proof Minimization and Interpolation Techniques” , Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD) , Nov. 2010

5. Chun-Nan Chou, Chang-Hong Hsu, Yueh-Tung Chao and Chung-Yang (Ric) Huang, “Formal Deadlock Checking on High-Level SystemC Designs” , Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD) , Nov. 2010

6. Hu-Hsi Yeh and Chung-Yang (Ric) Huang, “Automatic Constraint Generation for Guided Random Simulation” , Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) , Jan. 2010

7. Chin-Chia Nien, Shih-Heng Tsai, and Chung-Yang (Ric) Huang, “A Unified Multi-Corner Multi-Mode Static Timing Analysis Engine” , Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) , Jan. 2010

8. Kuen-Huei Lin, Siao-Jie Cai, and Chung-Yang (Ric) Huang, “Speeding Up SoC Virtual Platform Simulation by Data-Dependency-Aware Synchronization and Scheduling” , Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASP-DAC) , Jan. 2010

9. Chih-Jen Hsu, Shao-Lun Huang, Chia-An Wu and Chung-Yang (Ric) Huang, “Interpolant Generation without Constructing Resolution Graph” , Proc. IEEE/ACM International Conference on Computer-Aided Design (ICCAD) , Nov. 2009

10. Shih-Heng Tsai and Chung-Yang (Ric) Huang, “A False-Path Aware Formal Static Timing Analyzer Considering Simultaneous Input Transitions” , IEEE/ACM Design Automation Conference (DAC) , Jun. 2009

11. Chi-An Wu, Ting-Hao Lin, Shao-Lun Huang, and Chung-Yang (Ric) Huang, “SAT-Controlled Redundancy Addition and Removal - A Novel Circuit Restructuring Technique” , Asia and South Pacific Design Automation Conference (ASP-DAC) , Yokohama, Japan , Jan. 2009

12. Kuen-Huei Lin, Siao-Jie Cai, and Chung-Yang (Ric) Huang, “Speeding Up SoC Virtual Platform Simulation by Data-Dependency Aware Virtual Synchronization” , International SoC Design Conference (ISoCC) , Korea , Nov. 2008

13. Chao-Yue (Colby) Lai, Chung-Yang (Ric) Huang, and Kei-Yong Khoo, “Improving Constant-Coefficient Multiplier Verification by Partial Product Identification” , Design Automation and Test in Europe (DATE) , Munich, Germany , Mar. 2008

14. Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang (Ric) Huang, and A. Mishchenko, “Scalable Exploration of Functional Dependency by Interpolation and Incremental SAT Solving” , IEEE/ACM International Conference on Computer-Aided Design (ICCAD) , San Jose, USA , Nov. 2007

15. Hsing-Chih Hung, Chi-Wen Chang, Tin-Hao Lin, and Chung-Yang (Ric) Huang, “QuteIP: An IP Qualification Framework for System on Chip” , IEEE SoC Conference (SOCC) , Hsin-Chu, Taiwan , Aug. 2007

16. Chi-An Wu, Ting-Hao Lin, Chih-Chun Lee and Chung-Yang (Ric) Huang, “QuteSAT: A Robust Circuit-based SAT Solver for Complex Circuit Structure” , Design Automation and Test in Europe (DATE) Conference , Nice, France , Apr. 2007

17. Feng Lu, Li-C. Wang, K-T. Cheng, and Ric C-Y. Huang, “A Circuit SAT Solver with Signal Correlation Guided Learning” , Proc. Design Automation & Test Conference , Europe , Mar. 2003

18. G. Parthasarathy, K-T. Cheng, C-Y Huang, “An Analysis of ATPG and SAT algorithms for Formal Verification” , Proc. International High Level Design Validation and Test Workshop , Nov. 2001

19. R.C.-Y. Huang, B. Yang, H.-C. Tsai, and K.-T. Cheng, “Static Property Checking Using ATPG vs. BDD Techniques” , Proc. International Test Conference , Oct. 2000

20. R.C.-Y. Huang and K.-T. Cheng, “Assertion Checking by Combined Word-level ATPG and Modular Arithmetic Constraint-Solving Techniques” , Proc. Design Automation Conference , pp. 118-123 , Jun. 2000

21. R.C.-Y. Huang and K.-T. Cheng, “Solving Constraint Satisfiability Problem for Automatic Generation of Design Verification Vectors” , Proc. International High Level Design Validation and Test Workshop , Nov. 1999

22. R.C.-Y. Huang and K.-T. Cheng, “A New Extended Finite State Machine (EFSM) Model for RTL Design Verification” , Proc. International High Level Design Validation and Test Workshop , Nov. 1998

23. R.C.-Y. Huang, Y. Wang, and K.-T. Cheng, “Libra - A Library-Independent Framework for Post-Layout Performance Optimization” , Proc. International Symposium on Physical Design , Apr. 1998

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Books:

1. L-T. Wang, K-T. Cheng, Y-W. Chang, C-Y. Huang, et. al., “Electronic Design Automation: Synthesis, Verification, and Test” , Elsevier Publisher , USA, Jan. 2009

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Patents:

1. Chung-Yang (Ric) Huang, “Solving Constraint Satisfiability Problem For Automatic Generation of Design Verification Vectors” , US. No. 7073143, Jul. 2006

2. Chung-Yang (Ric) Huang, “Non-Assignable Signal Support During Formal Verification Of Circuit Designs” , US, No. 6618841, Sep. 2003

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